K4S561633CRL75000 Samsung Semiconductor, K4S561633CRL75000 Datasheet

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K4S561633CRL75000

Manufacturer Part Number
K4S561633CRL75000
Description
Manufacturer
Samsung Semiconductor
Type
SDRAMr
Datasheet

Specifications of K4S561633CRL75000

Organization
16Mx16
Density
256Mb
Address Bus
13b
Access Time (max)
7/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3V
Package Type
CSP
Operating Temp Range
-25C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2.7V
Supply Current
130mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
K4S561633C-R(B)L/N/P
CMOS SDRAM
16Mx16
SDRAM 54CSP
(VDD/VDDQ 3.0V/3.0V or 3.3V/3.3V)
Revision 1.4
December 2002
Rev. 1.4 Dec. 2002

Related parts for K4S561633CRL75000

K4S561633CRL75000 Summary of contents

Page 1

... K4S561633C-R(B)L/N/P SDRAM 54CSP (VDD/VDDQ 3.0V/3.0V or 3.3V/3.3V) 16Mx16 Revision 1.4 December 2002 CMOS SDRAM Rev. 1.4 Dec. 2002 ...

Page 2

... K4S561633C-R(B)L/N 16Bit x 4 Banks Synchronous DRAM in 54CSP FEATURES • 3.0V & 3.3V power supply. • LVCMOS compatible with multiplexed address. • Four banks operation. • MRS cycle with address key programs. -. CAS latency (1 & 2 & 3). -. Burst length ( & Full page). -. Burst type (Sequential & Interleave). ...

Page 3

... Bottom View *2: Top View Max. 0.20 Encapsulant *1: Bottom View < Top View #A1 Ball Origin Indicator *1 > E > CMOS SDRAM *2 < Top View 54Ball(6x9) CSP DQ15 SSQ DDQ B DQ14 DQ13 V V DDQ SSQ C DQ12 DQ11 V V SSQ DDQ D DQ10 DQ9 V V DDQ SSQ ...

Page 4

... DDQ V 2 3ns 1MHz, V =0.9V 50 mV) A REF Symbol Min C 2.0 CLK C 2 2.0 ADD C 3.5 OUT CMOS SDRAM Value Unit -1.0 ~ 4.6 V -1.0 ~ 4.6 V -55 ~ +150 Max Unit Note 3 +0.3 V DDQ 0 0 Max Unit 4 ...

Page 5

... Input signals are changed one time during 20ns CKE V (min), CLK V (max Input signals are stable Page burst 4Banks Activated t = 2CLKs CCD t t (min CKE 0. DDQ SSQ) CMOS SDRAM Version -75 - 0.5 0.5 = 10ns 10ns 130 130 185 185 -R(B)L 800 -R(B)N -R(B)P Rev ...

Page 6

... RAS t (max) RAS t (min (min (min) DAL t (min (min) BDL t (min) CCD CAS latency=3 CAS latency=2 CAS latency=1 CMOS SDRAM =Commercial, Extended, Industrial Temperature) Value 2.4 / 0.4 0 DDQ tr/tf = 1/1 0 DDQ See Fig. 2 Output (Fig output load circuit Version -1H - 100 70 84 ...

Page 7

... Symbol Min Max Min 7.5 9.5 t 1000 C C 9 SAC - 2.5 2.5 t 2 2.0 2 1.0 1 SLZ 5 SHZ - CMOS SDRAM -1H -1L Unit Max Min Max 9.5 1000 1000 2.5 ns 2.5 2 2 Rev. 1.4 Dec. 2002 Note 1 1 ...

Page 8

... MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are the same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. ...

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