PI74AVC+16268K Pericom Semiconductor, PI74AVC+16268K Datasheet
![no-image](/images/manufacturer_photos/0/5/521/pericom_semiconductor_sml.jpg)
PI74AVC+16268K
Manufacturer Part Number
PI74AVC+16268K
Description
Manufacturer
Pericom Semiconductor
Datasheet
1.PI74AVC16268K.pdf
(11 pages)
Specifications of PI74AVC+16268K
Lead Free Status / Rohs Status
Not Compliant
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5
Product Features
• PI74AVC+16268 is designed for low-voltage operation,
• True ±24mA Balanced Drive @ 3.3V
• I
• 3.6 I/O Tolerant Inputs and Outputs
• All outputs contain a patented DDC
• Industrial operation: –40°C to +85°C
• Packaging: (Pb-free & Green available):
Logic Block Diagram
(Dynamic DriveControl) circuit that reduces noise without
degrading propagation delay.
V CC = 1.65V to 3.6V
– 56-pin 240 mil wide plastic TSSOP (A)
OFF
06-0166
supports partial power-down operation
CLKEN1B
CLKENA1
CLKENA2
CLKEN2B
OEA
OEB
SEL
A1
CLK
8
1
29
27
30
55
56
28
2
C1
1D
1 of 12 Channels
1D
C1
CE
1D
C1
G1
1
1
1
Product Description
The PI74AVC+16268, a 12-bit to 24-bit registered bus exchanger
designed for 1.65V to 3.6V V
in which data must be transferred from a narrow high-speed bus to
a wide, lower frequency bus. It provides synchronous data exchange
between the two ports. Data is stored in internal registers on the low-
to-high transition of the clock (CLK) input when appropriate clock-
enable (CLKEN) inputs are low. The select (SEL) line is synchronous
with CLK and selects 1B or 2B input data for the A outputs.
For data transfer in the A-to-B direction, a two-stage pipeline is
provided in the A-to-1B path, with a single storage register in the
A-to-2B path. Proper control of these inputs allows two sequential
12-bit words to be presented synchronously as a 24-bit word on the
B-port. Data flow is controlled by the active-low output enables
(OEA, OEB). These control terminals are registered so bus direction
changes are synchronous with CLK.
To ensure the high-impedance state during power up or power
down, a clock pulse should be applied as soon as possible and OE
should be tied to V
of the resistor is determined by the current-sinking capability of the
driver. Because OE is being routed through a register, the active
state of the outputs cannot be determined prior to the arrival of the
first clock pulse.
Exchanger with 3-State Outputs
1D
CE
CE
1D
CE
1D
12-Bit to 24-Bit Registered Bus
CE
CC
C1
C1
C1
C1
C1
1D
1D
through a pullup resistor, the minimum value
CC
operation, is used for applications
PI74AVC+16268
23
6
1
B
2
1
B
1
PS8551A
06/01/06
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PI74AVC+16268K Summary of contents
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... Notes: • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • Pb-free & Green • Adding an X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 06-0166 .236 .244 .547 13.9 .555 14.1 .047 1.20 Max. .007 .002 .011 .006 ...