AD9445-BB-LVDS/PCB Analog Devices Inc, AD9445-BB-LVDS/PCB Datasheet - Page 12

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AD9445-BB-LVDS/PCB

Manufacturer Part Number
AD9445-BB-LVDS/PCB
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9445-BB-LVDS/PCB

Lead Free Status / Rohs Status
Not Compliant
AD9445
Pin No.
83
84
85
86
89
90
100
D12−
D12+
D13−
D13+ (MSB)
OR−
OR+
RF ENABLE
Mnemonic
Description
D12 Complement Output Bit.
D12 True Output Bit.
D13 Complement Output Bit.
D13 True Output Bit.
RF ENABLE Control Pin. CMOS-compatible control pin to optimize the configuration of
the AD9445 analog front end. Connecting RF ENABLE to AGND optimizes SFDR
performance for applications with analog input frequencies <210 MHz for 125 MSPS
speed grade and <230 MHz for the 105 MSPS speed grade. For applications with analog
inputs >225 MHz for the 125 MSPS speed grade and >230 MHz for the 105 MSPS speed
grade, this pin should be connected to AVDD1 for optimum SFDR performance. Power
dissipation from AVDD2 increases by 150 mW to 200 mW.
Out-of-Range Complement Output Bit.
Out-of-Range True Output Bit.
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