72V285L15PFI Integrated Device Technology (Idt), 72V285L15PFI Datasheet - Page 24

• Manufacturer Part Number: 72V285L15PFI
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 18 64-Pin TQFP Tray
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72V285L15PFI

• Package: 64TQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 1.125 Mb
• Organization: 64Kx18
• Data Bus Width: 18 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: -40 to 85 °C

FIFO in the chain to go LOW after a word has been read from the last FIFO is
the sum of the delays for each individual FIFO:
where N is the number of FIFOs in the expansion and T
period. Note that extra cycles should be added for the possibility that the t
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO
32,768 x 18 and 65,536 x 18
FWFT/SI
WRITE ENABLE
INPUT READY
DATA IN
WRITE CLOCK
For a full expansion configuration, the amount of time it takes for IR of the first
n
(N – 1)*(3*transfer clock) + 2 T
Dn
WEN
IR
WCLK
Figure 20. Block Diagram of 65,536 x 18 and 131,072 x 18 Depth Expansion
FWFT/SI
72V275
72V285
IDT
•
TRANSFER CLOCK
WCLK
RCLK
REN
OE
TM
OR
Qn
WCLK
is the WCLK
SKEW1
•
GND
n
24
specification is not met between RCLK and transfer clock, or WCLK and transfer
clock, for the IR flag.
is faster. Both these actions result in data moving, as quickly as possible, to the
end of the chain and free locations to the beginning of the chain.
The Transfer Clock line should be tied to either WCLK or RCLK, whichever
WCLK
IR
Dn
WEN
FWFT/SI
72V275
72V285
IDT
COMMERCIAL AND INDUSTRIAL
RCLK
REN
OR
OE
Qn
TEMPERATURE RANGES
OUTPUT ENABLE
n
OUTPUT READY
READ ENABLE
READ CLOCK
DATA OUT
4512 drw 23