72T36125L4-4BB Integrated Device Technology (Idt), 72T36125L4-4BB Datasheet - Page 8

• Manufacturer Part Number: 72T36125L4-4BB
• Description: FIFO Mem Async/Sync Dual Depth/Width Uni-Dir 256K x 36 240-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T36125L4-4BB

• Package: 240BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 9 Mb
• Organization: 256Kx36
• Data Bus Width: 36 Bit
• Timing Type: Asynchronous|Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: 0 to 70 °C

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
PIN DESCRIPTION (CONTINUED)
PRS
Q
RCLK/
RD
RCS
REN
RHSTL
RT
SCLK
SEN
SHSTL System HSTL
TCK
TDI
TDO
TMS
TRST
WEN
WCS
WCLK/
WR
Symbol
0
–Q
(2)
(2)
(2)
(2)
35
(2)
(1)
Partial Reset
Data Outputs
Read Clock/
Read Stobe
Read Chip Select
Read Enable
Read Port HSTL
Select
Retransmit
Serial Clock
Serial Enable
Select
JTAG Clock
JTAG Test Data
Input
JTAG Test Data
Output
JTAG Mode
Select
JTAG Reset
Write Enable
Write Chip Select
Write Clock/
Write Strobe
Name
HSTL-LVTTL PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,
HSTL-LVTTL Data outputs for an 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, any unused output pins should not
HSTL-LVTTL RCS provides synchronous control of the read port and output impedance of Qn, synchronous to RCLK. During
HSTL-LVTTL If Synchronous operation of the read port has been selected, REN enablesRCLK for reading data from the
HSTL-LVTTL RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to
HSTL-LVTTL A rising edge on SCLK will clock the serial data present on the SI input into the offset registers providing that
HSTL-LVTTL SEN enables serial loading of programmable flag offsets.
HSTL-LVTTL Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations
HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,
HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,
HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the
HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically
HSTL-LVTTL When Synchronous operation of the write port has been selected, WEN enables WCLK for writing data into
HSTL-LVTTL The WCS pin can be regarded as a second WEN input, enabling/disabling write operations.
HSTL-LVTTL If Synchronous operation of the write port has been selected, when enabled by WEN, the rising edge of WCLK
HSTL-LVTTL If Synchronous operation of the read port has been selected, when enabled by REN, the rising edge of RCLK
OUTPUT
OUTPUT
I/O TYPE
INPUT
INPUT
INPUT
INPUT
LVTTL
INPUT
INPUT
INPUT
LVTTL
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings
are all retained.
be connected. Outputs are not 5V tolerant regardless of the state of OE and RCS.
reads data from the FIFO memory and offsets from the programmable registers. If LD is LOW, the values
loaded into the offset registers is output on a rising edge of RCLK.If Asynchronous operation of the read
port has been selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. REN
should be tied LOW.
a Master Reset or Partial Reset the RCS input is don’t care, if OE is LOW the data outputs will be Low-Impedance
regardless of RCS.
FIFO memory and offset registers. If Asynchronous operation of the read port has been selected, the REN
input should be tied LOW.
This pin is used to select HSTL or 2.5v LVTTL outputs for the FIFO. If HSTL or eHSTL outputs are
required, this input must be tied HIGH. Otherwise it should be tied LOW.
HIGH in FWFT mode) and doesn’t disturb the write pointer, programming method, existing timing mode
or programmable flag settings. If a mark has been set via the MARK input pin, then the read pointer will jump
to the ‘mark’ location.
SEN is enabled.
INPUT
All inputs not associated with the write or read port can be selected for HSTL operation via the SHSTL input.
of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and
outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.
test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register
and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID
Register and Bypass Register. This output is high impedance except when shifting, while in SHIFT-DR and
SHIFT-IR controller states.
the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles.
If the TAP controller is not properly reset then the FIFO outputs will always be in high-impedance. If the JTAG
function is used but the user does not want to use TRST, then TRST can be tied with MRS to ensure proper
FIFO operation. If the JTAG function is not used then this signal needs to be tied to GND.
theFIFO memory and offset registers. If Asynchronous operation of the write port has been selected, the
WEN input should be tied LOW.
writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into
the FIFO on a rising edge in an Asynchronous manner, (WEN should be tied to its active state).
8
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 4, 2009