ISPLSI 2064E-100LT100 Lattice, ISPLSI 2064E-100LT100 Datasheet - Page 8

• Manufacturer Part Number: ISPLSI 2064E-100LT100
• Description: CPLD ispLSI® 2000E Family 2K Gates 64 Macro Cells 100MHz EECMOS Technology 5V 100-Pin TQFP
• Manufacturer: Lattice

Specifications of ISPLSI 2064E-100LT100

• Package: 100TQFP
• Family Name: ispLSI® 2000E
• Device System Gates: 2000
• Maximum Propagation Delay Time: 13 ns
• Number Of User I/os: 64
• Number Of Logic Blocks/elements: 16
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 100 MHz
• Operating Temperature: 0 to 70 °C

I CC can be estimated for the ispLSI 2064E using the following equation:
I CC (mA) = 7 + (# of PTs * 0.75) + (# of nets * Max freq * 0.004)
Where:
The I CC estimate is based on typical conditions (V CC = 5.0V, room temperature) and an assumption of two GLB loads on
average exists. These values are for estimates only. Since the value of I CC is sensitive to operating conditions and the
program in the device, the actual I CC should be verified.
Power consumption in the ispLSI 2064E device depends
on two primary factors: the speed at which the device is
operating and the number of Product Terms used.
Figure 3. Typical Device Power Consumption vs fmax
Power Consumption
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
160
150
140
130
120
110
100
90
80
70
1
20
40
Notes: Configuration of Four 16-bit Counters
60
Typical Current at 5V, 25° C
80
f
max (MHz)
8
Figure 3 shows the relationship between power and
operating speed.
100 120 140 160 180 200
Specifications ispLSI 2064E
ispLSI 2064E
0127A/2064E