MT9172AP1 Zarlink, MT9172AP1 Datasheet - Page 12

• Manufacturer Part Number: MT9172AP1
• Description: Digital Network Interface Circuit 28-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT9172AP1

• Package: 28PLCC
• Maximum Data Rate: 160 Kbps
• Transmission Media Type: Twisted Pair
• Power Supply Type: Analog
• Typical Supply Current: 10 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

Notes:
1.
2.
Notes:
3
4.
.
2,3
Bit
Bit
C-Channel
XXX01111
Default Mode 1 can also be selected by tying CDSTi/CDi pin low when DNIC is operating in dual mode.
Default Mode 2 can also be selected by tying CDSTi/CDi pin high when DNIC is operating in dual mode.
6
7
Suggested use of ATTACK:
-At 160 kbit/s full convergence requires 850 ms with ATTACK held high for the first 240 frames or 30 ms.
-At 80 kbit/s full convergence requires 1.75 s with ATTACK held high for the first 480 frames or 60 ms.
When bits 4-7 of the Control Register are all set to one, the DNIC operates in one of the default modes as defined in Table 4a,
depending upon the status of bit-3.
XXX11111
0
1
(Bit 0-7)
Reg Sel-1
Reg Sel-1
ATTACK
bit 0
TxHK
bit 0
Name
Reg Sel-1
Reg Sel-2
Loopback
Name
Internal Control
2
2
00000000
00010000
Reg Sel-2
Reg Sel-2
Register
bit 1
bit 1
Convergence Speedup. When set to ’1’, the echo canceller will converge to the reflection
coefficient much faster. Used on power-up for fast convergence.
canceller will require the normal amount of time to converge to a reflection coefficient.
Transmit Housekeeping. When set to ’0’, logic zero is transmitted over the line as
Housekeeping Bit. When set to ’1’, logic one is transmitted over the line as
Housekeeping Bit.
Register Select-1. Must be set to ’0’ to select the Diagnostic Register.
Register Select-2. Must be set to ’1’ to select the Diagnostic Register.
Bit 2
0
0
1
1
DRR
bit 2
bit 2
Bit 3
Internal Diagnostic
0
1
0
1
Loopback
Table 4a - Default Mode Selection
01000000
01000000
Table 4 - Control Register
Register
All loopback testing functions disabled. Normal operation.
DSTi internally looped back into DSTo for system diagnostics.
L
DSTo is internally looped back into DSTi for end-to-end testing.
Zarlink Semiconductor Inc.
OUT
bit 3
bit 3
BRS
MT9171/72
is internally looped back into L
12
DINB
bit 4
FUN
bit 4
Default Mode-1
PSEN, DINB, DRR and all diagnostics are disabled.
TxHK=0.
Default Mode-2
PSEN, DINB, DRR and all diagnostics are disabled.
TxHK=0.
Default Mode Selection (Refer to Table 4a)
Description
Description
Default Mode Selection
PSWAP
PSEN
(Refer to Table 4a)
bit 5
bit 5
3
4
: Bit rate is 80 kbit/s. ATTACK,
Bit rate is 160 kbit/s. ATTACK,
Description
IN
ATTACK
for system diagnostics.
bit 6
DLO
bit 6
1
When ’0’, the echo
Not Used
TxHK
bit 7
bit 7
Data Sheet
2
3