FTLF1721P1BCL Finisar Corporation, FTLF1721P1BCL Datasheet - Page 7

• Manufacturer Part Number: FTLF1721P1BCL
• Description: 1310NM DFB, APD, OC-48 LR-1, GIGE, 1X/2X FC, 2.67 GB/S MULTI
• Manufacturer: Finisar Corporation

Specifications of FTLF1721P1BCL

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

F i n i s a r
FTLF1721P1xCL Pluggable SFP Product Specification – September 2008
Additionally, Finisar SFP transceivers provide a unique enhanced digital diagnostic
monitoring interface, which allows real-time access to device operating parameters such
as transceiver temperature, laser bias current, transmitted optical power, received optical
power and transceiver supply voltage. It also defines a sophisticated system of alarm and
warning flags, which alerts end-users when particular operating parameters are outside of
a factory set normal range.
2
The SFP MSA defines a 256-byte memory map in E
PROM that is accessible over a
2-wire serial interface at the 8 bit address 1010000X (A0h). The digital diagnostic
monitoring interface makes use of the 8 bit address 1010001X (A2h), so the originally
defined serial ID memory map remains unchanged. The interface is identical to, and is
thus fully backward compatible with both the GBIC Specification and the SFP Multi
Source Agreement. The complete interface is described in Finisar Application Note AN-
2030: “Digital Diagnostics Monitoring Interface for SFP Optical Transceivers”.
The operating and diagnostics information is monitored and reported by a Digital
Diagnostics Transceiver Controller (DDTC) inside the transceiver, which is accessed
through a 2-wire serial interface. When the serial protocol is activated, the serial clock
signal (SCL, Mod Def 1) is generated by the host. The positive edge clocks data into the
2
SFP transceiver into those segments of the E
PROM that are not write-protected. The
negative edge clocks data from the SFP transceiver. The serial data signal (SDA, Mod
Def 2) is bi-directional for serial data transfer. The host uses SDA in conjunction with
SCL to mark the start and end of serial protocol activation. The memories are organized
as a series of 8-bit data words that can be addressed individually or sequentially.
1
For more information, please see the SFP MSA documentation
or Finisar Application
Note AN-2030.
© Finisar Corporation September 3, 2008 RevA.1
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