LFE2M20SE-5FN256I Lattice, LFE2M20SE-5FN256I Datasheet - Page 21

• Manufacturer Part Number: LFE2M20SE-5FN256I
• Description: FPGA LatticeECP2M Family 19000 Cells 90nm (CMOS) Technology 1.2V 256-Pin FBGA
• Manufacturer: Lattice

Specifications of LFE2M20SE-5FN256I

• Package: 256FBGA
• Family Name: LatticeECP2M
• Device Logic Units: 19000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 140
• Ram Bits: 1246208
• In System Programmability: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-18. Slice0 through Slice2 Control Selection
Edge Clock Routing
LatticeECP2/M devices have a number of high-speed edge clocks that are intended for use with the PIOs in the
implementation of high-speed interfaces. There are eight edge clocks per device: two edge clocks per edge. Differ-
ent PLL and DLL outputs are routed to the two muxes on the left and right sides of the device. In addition, the
CLKO signal (generated from the DLLDELA block) is routed to all the edge clock muxes on the left and right sides
of the device. Figure 2-19 shows the selection muxes for these clocks.
Figure 2-19. Edge Clock Mux Connections
Secondary Clock
GPLL Output CLKOP
GPLL Output CLKOS
DLL Output CLKOP
DLL Output CLKOS
Clock Input Pad
GPLL Input Pad
GPLL Input Pad
Routing
Vcc
Input Pad
Input Pad
Routing
Routing
Routing
CLKO
CLKO
12
3
1
2-18
16:1
Top and Bottom
ECLK1/ ECLK2
Left and Right
Left and Right
Edge Clocks
Edge Clocks
Edge Clocks
(Both Mux)
LatticeECP2/M Family Data Sheet
ECLK1
ECLK2
Slice Control
Architecture