XC3S100E-4TQ144C Xilinx Inc, XC3S100E-4TQ144C Datasheet - Page 97
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XC3S100E-4TQ144C
Manufacturer Part Number
XC3S100E-4TQ144C
Description
FPGA Spartan®-3E Family 100K Gates 2160 Cells 572MHz 90nm (CMOS) Technology 1.2V 144-Pin TQFP
Manufacturer
Xilinx Inc
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S100E-4TQ144C
Package
144TQFP
Family Name
Spartan®-3E
Device Logic Cells
2160
Device Logic Units
240
Device System Gates
100000
Number Of Registers
1920
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
108
Ram Bits
73728
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Table 65: Slave Parallel Mode Connections (Continued)
Voltage Compatibility
FPGA’s I/O Bank 2, supplied by the VCCO_2 supply input.
The VCCO_2 voltage can be 1.8V, 2.5V, or 3.3V to match
the requirements of the external host, ideally 2.5V. Using
1.8V or 3.3V requires additional design considerations as
the DONE and PROG_B pins are powered by the FPGA’s
2.5V V
tion of Spartan-3 FPGAs for additional information.
DS312-2 (v3.8) August 26, 2009
Product Specification
INIT_B
DONE
PROG_B
V
Pin Name
Most Slave Parallel interface signals are within the
CCAUX
R
supply. See XAPP453: The 3.3V Configura-
FPGA Direction
bidirectional I/O
bidirectional I/O
Open-drain
Open-drain
Input
Initialization Indicator. Active Low.
Goes Low at the start of
configuration during the Initialization
memory clearing process. Released
at the end of memory clearing, when
mode select pins are sampled. In
daisy-chain applications, this signal
requires an external 4.7 kΩ pull-up
resistor to VCCO_2.
FPGA Configuration Done. Low
during configuration. Goes High
when FPGA successfully completes
configuration. Requires external
330 Ω pull-up resistor to 2.5V.
Program FPGA. Active Low. When
asserted Low for 500 ns or longer,
forces the FPGA to restart its
configuration process by clearing
configuration memory and resetting
the DONE and INIT_B pins once
PROG_B returns High.
Recommend external 4.7 kΩ pull-up
resistor to 2.5V. Internal pull-up
value may be weaker (see
Table
3.3V output, use an open-drain or
open-collector driver or use a
current limiting series resistor.
78). If driving externally with a
Description
www.xilinx.com
Daisy-Chaining
If the application requires multiple FPGAs with different con-
figurations, then configure the FPGAs using a daisy chain.
Use Slave Parallel mode (M[2:0] = <1:1:0>) for all FPGAs in
the daisy-chain. The schematic in
FPGA downloading and does not support the SelectMAP
read interface. The FPGA’s RDWR_B pin must be Low dur-
ing configuration.
After the lead FPGA is filled with its configuration data, the
lead FPGA enables the next FPGA in the daisy-chain by
asserting is chip-select output, CSO_B.
Active during configuration. If
CRC error detected during
configuration, FPGA drives
INIT_B Low.
Low indicates that the FPGA is
not yet configured.
Must be High to allow
configuration to start.
During Configuration
Figure 62
Functional Description
User I/O. If unused in the
application, drive INIT_B
High.
Pulled High via external
pull-up. When High,
indicates that the FPGA
successfully configured.
Drive PROG_B Low and
release to reprogram
FPGA.
After Configuration
is optimized for
97
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