LE58QL063HVC Zarlink, LE58QL063HVC Datasheet - Page 39

• Manufacturer Part Number: LE58QL063HVC
• Description: SLIC 4-CH 3.3V 64-Pin LQFP Tray
• Manufacturer: Zarlink

Specifications of LE58QL063HVC

• Package: 64LQFP
• Number Of Channels Per Chip: 4
• Polarity Reversal: Yes
• Minimum Operating Supply Voltage: 3.135 V
• Typical Operating Supply Voltage: 3.3 V

The frame synchronization signal (FSC) identifies GCI channel 0 and all GCI channels are referenced to it.
Upstream Data is always transmitted at a 2.048 MHz data rate.
Receive Signal Processing
In the receive path (D/A), the digital signal is expanded (for A-law or µ-law), filtered, converted to analog, and passed to the VOUT
pin. The signal processor contains an ALU, RAM, ROM, and Control logic to implement the filter sections. The Z, R, and GR
blocks are user-programmable filter sections with their coefficients stored in the coefficient RAM, while AR is an analog amplifier
which can be programmed for a 0 dB or 6.02 dB loss. The Z, R, and GR filters can also be operated from an alternate set of
default coefficients stored in ROM (MPI Command 60/61h, GCI Command SOP 7).
The low-pass filter band limits the signal. The R filter is composed of a six-tap FIR section operating at a 16 kHz sampling rate and
a one-tap IIR section operating at 8 kHz. It is part of the frequency response correction network. The Analog Impedance Scaling
Network (AISN) is a user-programmable gain block providing feedback from VIN to VOUT to emulate different SLIC device input
impedances from a single external SLIC device impedance. The Z filter provides feedback from the transmit signal path to the
receive path and is used to modify the effective input impedance to the system. The interpolator increases the sampling rate prior
to
D/A conversion.
Receive PCM Interface (PCM/MPI Mode)
The receive PCM interface logic controls the reception of data bytes from the PCM highway, transfers the data to the A-law or µ-
law expansion logic for compressed signals, and then passes the data to the receive path of the signal processor. If the data
received from the PCM highway is programmed for linear code, the A-law or µ-law expansion logic is bypassed and the data is
presented to the receive path of the signal processor directly. The linear data requires two consecutive time slots, while the A-
law or µ-law data requires a single time slot.
The frame sync (FS) pulse identifies time slot 0 of the receive frame, and all channels (time slots) are referenced to it. The logic
contains user-programmable Receive Time Slot and Receive Clock Slot registers. The Time Slot register is 7 bits wide and allows
up to 128 8-bit channels (using a PCLK of 8.192 MHz) in each frame. This feature allows any clock frequency between 128 kHz
and 8.192 MHz (2 to 128 channels) in a system.
The Clock Slot register is 3 bits wide and can be programmed to offset the time slot assignment by 0 to 7 PCLK periods to
eliminate any clock skews in the system. An exception occurs when division of the PCLK frequency by 64 kHz produces a
nonzero remainder (R), and when the receive clock slot is greater than R. In this case, the last full receive time slot in the frame
is not usable. For example, if the PCLK frequency is 1.544 MHz (R = 1), the receive clock slot can be only 0 or 1 if the last time
slot is to be used. The PCM data can be user-programmed for input from either the DRA or DRB port.
Data Downstream Interface (GCI Mode)
The Data Downstream (DD) interface logic controls the reception of data bytes from the GCI highway. The GCI channels received
by the QLSLAC device is determined by the logic levels on S0 and S1, the GCI channel select bits. The two compressed voice
channel data bytes of the GCI channel are transferred to the A-law or µ-law expansion logic. The expanded data is passed to the
receive path of the signal processor. The Monitor channel and SC channel bytes are transferred to the GCI control logic for
processing.
The frame synchronization signal (FSC) identifies GCI channel 0 of the GCI frame, and all other GCI channels are referenced to it.
Downstream Data is always received at a 2.048 MHz data rate.
Analog Impedance Scaling Network (AISN)
The AISN is incorporated in the QLSLAC device to scale the value of the external SLIC device impedance. Scaling this external
impedance with the AISN (along with the Z filter) allows matching of many different line conditions using a single impedance
value. Line cards can meet many different specifications without any hardware changes.
The AISN is a programmable transfer function connected from VIN to VOUT of each QLSLAC device channel. The AISN transfer
function can be used to alter the input impedance of the SLIC device to a new value (Z
where G
SLIC device input impedance without the QLSLAC device.
440
is the SLIC device echo gain into an open circuit, G
Z
IN
=
Z
SL
•
(
1 G
Zarlink Semiconductor Inc.
–
44
•
h
39
44
AISN
is the SLIC device echo gain into a short circuit, and Z
) ⁄ 1 G
(
–
440
• h
AISN
IN
)
) given by:
SL
is the