LC5512MB-75F256I Lattice, LC5512MB-75F256I Datasheet - Page 48

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LC5512MB-75F256I

Manufacturer Part Number
LC5512MB-75F256I
Description
LATLC5512MB-75F256I 512MC CPLD 150K Gate
Manufacturer
Lattice
Datasheet

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Lattice Semiconductor
Switching Test Conditions
Figure 21 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are shown in Table 14.
Figure 21. Output Test Load, LVTTL and LVCMOS Standards
Table 14. Test Fixture Required Components
Default LVCMOS 1.8 I/O (L -> H, H -> L)
LVCMOS I/O (L -> H, H -> L)
Default LVCMOS 1.8 I/O (Z -> H)
Default LVCMOS 1.8 I/O (Z -> L)
Default LVCMOS 1.8 I/O (H -> Z)
Default LVCMOS 1.8 I/O (L -> Z)
Note: Output test conditions for all other interfaces are determined by the respective standards.
Test Condition
Device
Output
*C
L
includes test fixture and probe capacitance.
106
106
106
R
1
106
106
106
R
2
V
R 1
R 2
35pF
35pF
35pF
48
35pF
5pF
5pF
CCO
C
L
LVCMOS2.5 = V
LVCMOS1.8 = V
C L *
LVCMOS3.3 = 1.5V
ispXPLD 5000MX Family Data Sheet
Timing Ref.
V
V
OL
OH
V
V
V
CCO
CCO
CCO
+ 0.15
- 0.15
Point
/2
/2
/2
Test
CCO
CCO
/2
/2
LVCMOS1.8 = 1.65V
LVCMOS3.3 = 3.0V
LVCMOS2.5 = 2.3V
1.65V
1.65V
1.65V
1.65V
V
1.8V
CCO

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