MT90820AP1 Zarlink, MT90820AP1 Datasheet - Page 15

• Manufacturer Part Number: MT90820AP1
• Description: PB FREE LARGE DIGITAL SWITCH
• Manufacturer: Zarlink

1 - 0
15 - 13
Bit
3
2
DR1
Bit
12
11
0
0
1
1
15
15
0
0
Read/Write Address:
Reset Value:
Read Address:
Reset Value:
14
14
DR1-0
0
Name
0
OSB
SFE
DR0
0
1
0
1
Unused
Name
FD11
13
CFE
13
0
0
Table 9 - Serial Data Rate Selection (16 input x 16 output)
CFE
12
12
Output Stand By. When ODE = 0 and OSB = 0, the output drivers of STo0 to STo15 are in
high impedance mode. When ODE = 0 and OSB = 1, the output driver of STo0 to STo15
function normally. When ODE = 1, STo0 to STo15 output drivers function normally.
Start Frame Evaluation. A zero to one transition in this bit starts the frame evaluation
procedure. When the CFE bit in the FAR register changes from zero to one, the evaluation
procedure stops. To start another frame evaluation cycle, set this bit to zero for at least one
frame.
Data Rate Select. Input/Output data rate selection. See Table 9 for detailed programming.
0
Table 8 - Interface Mode Selection (IMS) Register Bits
FD11
11
11
Must be zero for normal operation.
Complete Frame Evaluation. When CFE = 1, the frame evaluation is completed and
bits FD10 to FD0 bits contains a valid frame alignment offset.
This bit is reset to zero, when SFE bit in the IMS register is changed from 1 to 0.
Frame Delay Bit 11. The falling edge of FE (or rising edge for GCI mode) is sampled
during the CLK-high phase (FD11 = 1) or during the CLK-low phase (FD11 = 0). This
bit allows the measurement resolution to 1/2 CLK cycle.
0
01
0000
02
0000
H
H
Data Rate Selected
FD10
10
,
,
10
H
H
0
.
.
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
Reserved
BPD
FD9
4
Zarlink Semiconductor Inc.
9
9
MT90820
BPD
FD8
8
3
8
15
BPD
FD7
7
2
7
Description
BPD
FD6
6
1
6
Description
BPD
FD5
5
0
5
BPE
FD4
4
4
Master Clock Required
OSB
FD3
3
3
16.384 MHz
4.096 MHz
8.192 MHz
Reserved
SFE
FD2
2
2
DR1
FD1
1
1
Data Sheet
DR0
FD0
0
0