MAX509ACAP Maxim Integrated Products, MAX509ACAP Datasheet - Page 4

• Manufacturer Part Number: MAX509ACAP
• Description: IC DAC QUAD SERIAL 8BIT 20-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX509ACAP

• Settling Time: 6µs
• Number Of Bits: 8
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 800mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ELECTRICAL CHARACTERISTICS (continued)
(V DD = +5V ±10%, V SS = 0V to -5.5V, V REF = 4V, AGND = DGND = 0V, R L = 10kΩ, C L = 100pF, T A = T MIN to T MAX ,
unless otherwise noted.)
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
TIMING CHARACTERISTICS
(V DD = +5V ±10%, V SS = 0V to -5V, V REF = 4V, AGND = DGND = 0V, C L = 50pF, T A = T MIN to T MAX , unless otherwise noted.)
Note 7: Guaranteed by design.
Note 8: If LDAC is activated prior to CS's rising edge, it must stay low for t
Note 9: Minimum delay from 12th clock cycle to CS rise.
4
Note 1: Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex.
Note 2: Input capacitance is code dependent. The highest input capacitance occurs at code = 00 hex.
Note 3: VREF = 4V
Note 4: VREF = 4V
Note 5: Guaranteed by design.
Note 6: Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex.
POWER SUPPLIES
SERIAL INTERFACE TIMING
Positive Supply Voltage
Negative Supply Voltage
Positive Supply Current
Negative Supply Current
LDAC Pulse Width Low
CS Rise to LDAC Fall Setup Time
CLR Pulse Width Low
CS Fall to SCLK Setup Time
SCLK Fall to CS Rise Hold Time
SCLK Rise to CS Rise Hold Time
SCLK Fall to CS Fall Hold Time
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
SCLK Clock Frequency
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK to DOUT Valid
_______________________________________________________________________________________
code of all other DACs to 00 hex.
PARAMETER
PARAMETER
p-p
p-p
, 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the
, 10kHz. DAC code = 00 hex.
SYMBOL
SYMBOL
t
t
t
t
t
V
t
CSH2
CSH1
CSH0
f
t
V
I
LDW
CLW
t
t
t
I
CSS
t
CLK
t
CLL
DD
DH
CH
DO
SS
DS
CL
DD
SS
For specified performance
For specified performance
Outputs unloaded, all
digital inputs = 0V or V
V
unloaded, all digital
inputs = 0V or V
MAX5_ _C/E
MAX5_ _M
(Notes 7, 8)
MAX5_ _C/E
MAX5_ _M
MAX5_ _C/E
MAX5_ _M
(Note 9)
(Note 7)
MAX5_ _C/E
MAX5_ _M
MAX5_ _C/E
MAX5_ _M
MAX5_ _C/E
MAX5_ _M
MAX5_ _C/E
MAX5_ _M
MAX5_ _C/E
MAX5_ _M
SS
= -5V ±10%, outputs
CONDITIONS
CONDITIONS
DD
DD
LDW
MAX5_ _C/E
MAX5_ _M
MAX5_ _C/E
MAX5_ _M
or longer after CS goes high.
MIN
MIN
-5.5
4.5
40
50
40
50
40
50
40
40
50
40
50
40
50
10
10
0
0
0
0
TYP
TYP
20
25
20
25
20
20
5
5
5
5
MAX
MAX
12.5
5.5
100
100
10
12
10
12
10
0
UNITS
UNITS
MHz
mA
mA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V