A3950SEUTR-T Allegro, A3950SEUTR-T Datasheet - Page 3

• Manufacturer Part Number: A3950SEUTR-T
• Manufacturer: Allegro

A3950
Terminal List Table
ENABLE
NFAULT
PHASE
SENSE
SLEEP
MODE
VREG
Name
OUTB
OUTA
GND
VBB
VCP
CP1
CP2
Pad
NC
5 kΩ
V
DD
5 kΩ
2, 12
ENABLE
NFAULT
0.22 μF
25 V
EU
15
16
10
13
14
11
PHASE
SLEEP
1
3
4
6
7
8
9
5
–
MODE
VREG
Number
4,13
LP
10
11
12
14
15
16
1
2
3
5
6
7
8
9
–
Functional Block Diagram
Fault output, open drain
Logic input
Logic input for direction control
Ground
Logic input
Logic input
DMOS full-bridge output A
Power return
Load supply voltage
DMOS full-bridge output B
Charge pump capacitor terminal
Charge pump capacitor terminal
Reservoir capacitor terminal
Regulator decoupling terminal
No connection
Exposed pad for thermal dissipation connect to GND pins
GND
Control Logic
Gate Supply
Low-Side
UVLO
STB
STG
TSD Warning
DMOS Full-Bridge Motor Driver
Pad
CP1
Motor Lead
Supply
Protection
Bias
Charge
Description
GND
Pump
CP2
0.1 μF
VBB
OUTA
OUTB
SENSE
115 Northeast Cutoff, Box 15036
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com
SENSE
VCP
VBB
OUTA
OUTB
0.1 μF
0.1 μF
Load Supply
100 μF
3