88PG8227A1-NFE1C000 Marvell, 88PG8227A1-NFE1C000 Datasheet - Page 14

• Manufacturer Part Number: 88PG8227A1-NFE1C000
• Description: MVL88PG8227A1-NFE1C000 1 MHZ DUAL STEP D
• Manufacturer: Marvell

Table 3:
Doc. No. MV-S103563-00 Rev. C
Page 14
Pi n #
14
15
16
17
19
18, 20
P in N a m e
VSET2
PSET2
POR2
PVIN2
PGND2
SW2
Pin Descriptions
88PG82XX
Datasheet
Pi n Typ e
I
I
O
S
GND
O
Document Classification: Proprietary Information
P i n D es c r ip t i o n
Voltage Set for Regulator 2.
1. Resistor Programming: Connect an external resistor to ground to set the
2. Logic Programming: Four output voltage levels (0.8V, 1.0V, 1.2V, and 1.5V)
Percent Set for Regulator 2.
1. Resistor Programming: Connect an external resistor to ground to set the
2. Logic Programming: Four output voltage levels (0.8V, 1.0V, 1.2V, and 1.5V)
Power-On Reset 2.
This pin is an open drain output to indicate the status of the output voltage. The
output pin goes high 40 ms after the output voltage is within the specified
tolerance.
indicate “both output good”.
Power Input Voltage for regulator 2: Internal power MOSFET source. Connect
the 10 µF decoupling capacitor between PVIN2 and PGND2 and position it as
close as possible to the IC.
NOTE: PVIN and PVIN2 must be connected together and should not be
Power Ground for regulator 2: The power ground must be connected to the
negative terminal of the input and output capacitors.
Switch Node for regulator 2: Internal power MOSFET drain. Connects to an
external inductor.
POR2 and POR1 can be connected to the same external pull up resistor to
output voltage of the switching regulator. See the “Electrical
Characteristics” for resistor values and Output Voltage Settings. Use
resistor values with a tolerance of 5% or better. The total capacitance
across this pin and GND should be equal to 25 pF or less.
can be set by connecting the VSET and PSET pins to either GND or SVIN.
output voltage of the switching regulator. See the “Electrical
Characteristics” for resistor values and Output Voltage Settings. Use
resistor values with a tolerance of 5% or better. The total capacitance
across this pin and GND should be equal to 25 pF or less. If the pin is not
used, it must be connected to GND.
can be set by connecting the VSET and PSET pins to either GND or SVIN.
separated.
Copyright © 2008 Marvell
April 23, 2008, 2.00