MAX5733BUTN+T Maxim Integrated Products, MAX5733BUTN+T Datasheet - Page 10

• Manufacturer Part Number: MAX5733BUTN+T
• Description: IC DAC 16BIT 32CHAN SER 56-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX5733BUTN+T

• Settling Time: 20µs
• Number Of Bits: 16
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 32
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 2.5W
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
TIMING CHARACTERISTICS—DV
(Figures 2 and 3, AV
unless otherwise noted. Typical values are at T
TIMING CHARACTERISTICS—DV
(Figures 2 and 3, AV
unless otherwise noted. Typical values are at T
Note 9: The maximum clock frequency (f
10
Serial Clock Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Fall to CS Fall Setup Time
CS Fall to SCLK Fall Setup Time
CS Rise to SCLK Fall
SCLK Fall to CS Rise Setup Time
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
SCLK Fall to DOUT Fall
SCLK Fall to DOUT Rise
CS Pulse-Width High
CS Pulse-Width Low
LDAC Pulse-Width Low
CLR Pulse-Width Low
Serial Clock Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Fall to CS Fall Setup Time
CS Fall to SCLK Fall Setup Time
CS Rise to SCLK Fall
SCLK Fall to CS Rise Setup Time
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
SCLK Fall to DOUT Fall
SCLK Fall to DOUT Rise
CS Pulse-Width High
CS Pulse-Width Low
LDAC Pulse-Width Low
CLR Pulse-Width Low
______________________________________________________________________________________
PARAMETER
PARAMETER
DD
DD
= +4.75V to +5.25V, DV
= +4.75V to +5.25V, DV
SYMBOL
SYMBOL
t
t
t
t
CSPWH
CSPWH
CSPWL
CSPWL
t
t
f
f
t
t
t
LDAC
t
t
t
t
LDAC
t
SCLK
t
t
t
SCLK
t
t
t
t
t
SDH
t
SCS
CSS
t
t
SDH
CLR
t
SCS
CSS
CS1
CS2
t
SCL
CLR
t
CS1
CS2
SCL
SCLK
CH
DH
CH
DS
DH
CL
DS
CL
) is 10MHz in daisy-chain mode when DV
A
A
= +25°C.)
= +25°C.)
DD
DD
DD
DD
At end of cycle in SPI mode only
Load capacitance = 20pF
Load capacitance = 20pF
At end of cycle in SPI mode only
Load capacitance = 20pF (Note 9)
Load capacitance = 20pF (Note 9)
= +4.75V to +5.25V, AGND = DGND = REFGND = GS = 0, T
= +2.7V to +5.25V, AGND = DGND = REFGND = GS = 0, T
= +4.75V to +5.25V
= +2.7V to +5.25V
CONDITIONS
CONDITIONS
DD
< 4.75V.
MIN
MIN
10
10
15
10
50
20
20
20
10
10
10
10
18
10
50
20
20
20
0
6
5
0
2
0
0
2
TYP
TYP
A
A
MAX
MAX
= T
= T
25
35
35
33
20
20
MIN
MIN
to T
to T
UNITS
UNITS
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MAX
MAX
,
,