ATF1504BE-7AU44 Atmel, ATF1504BE-7AU44 Datasheet - Page 5

IC CPLD 64MC 1.8V 44-TQFP

ATF1504BE-7AU44

Manufacturer Part Number
ATF1504BE-7AU44
Description
IC CPLD 64MC 1.8V 44-TQFP
Manufacturer
Atmel
Series
ATF1504BEr
Datasheet

Specifications of ATF1504BE-7AU44

Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
1.7 V ~ 1.9 V
Number Of Macrocells
64
Number Of I /o
32
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Features
CMOS/TTL Compatible
Voltage
1.8V
Memory Type
CMOS
For Use With
ATF15XX-DK3 - KIT DEV FOR ATF15XX CPLD'S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATF1504BE-7AU44
Manufacturer:
Atmel
Quantity:
10 000
Figure 1-3.
3637B–PLD–1/08
I/O (MC64)/GCLK3
8 or 16
Block Diagram
Each of the 64 macrocells generates a buried feedback signal that goes to the global bus (see
Figure
block then selects 40 individual signals from the global bus. Each macrocell also generates a
foldback logic term that goes to a regional bus. Cascade logic between macrocells in the
ATF1504BE allows fast, efficient generation of complex logic functions. The ATF1504BE con-
tains eight such logic chains, each capable of creating sum term logic with a fan-in of up to 40
product terms.
The ATF1504BE macrocell, shown in
complex logic functions operating at high speed. The macrocell consists of five sections: product
terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select
and enable, and logic array inputs.
A security fuse, when programmed, protects the contents of the ATF1504BE. Two bytes
(16 bits) of User Electronic Signature are accessible to the user for purposes such as storing
project name, part number, revision or date. The User Electronic Signature is accessible regard-
less of the state of the security fuse.
The ATF1504BE device supports In-System Programming (ISP) via the industry-standard 4-pin
JTAG interface (IEEE 1532 standard), and is fully compliant with IEEE 1149.1 for Boundary
Scan Test. ISP allows the device to be programmed without removing it from the printed circuit
board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to
be made in the field via software.
1-3). Each input and I/O pin also feeds into the global bus. The switch matrix in each logic
8 or 16
Figure
1-4, is highly flexible and capable of supporting
ATF1504BE
5

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