ATF1504ASVL-20AU100 Atmel, ATF1504ASVL-20AU100 Datasheet - Page 5

• Manufacturer Part Number: ATF1504ASVL-20AU100
• Description: IC CPLD 20NS LOWV LOWPWR 100TQFP
• Manufacturer: Atmel
• Series: ATF1504ASV(L)r

Specifications of ATF1504ASVL-20AU100

• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 20.0ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Macrocells: 64
• Number Of I /o: 64
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Voltage: 3.3V
• Memory Type: EEPROM
• Number Of Product Terms Per Macro: 40
• Maximum Operating Frequency: 66 MHz
• Delay Time: 20 ns
• Number Of Programmable I/os: 64
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• For Use With: ATF15XX-DK3 - KIT DEV FOR ATF15XX CPLD'S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / Rohs Status: Details

Block Diagram
Product Terms and Select
Mux
1409J–PLD–6/05
Unused product terms are automatically disabled by the compiler to decrease power
consumption. A security fuse, when programmed, protects the contents of the
ATF1504ASV(L). Two bytes (16 bits) of User Signature are accessible to the user for
purposes such as storing project name, part number, revision or date. The User Signa-
ture is accessible regardless of the state of the security fuse.
The ATF1504ASV(L) device is an in-system programmable (ISP) device. It uses the
industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully-compliant with
JTAG’s Boundary-scan Description Language (BSDL). ISP allows the device to be pro-
grammed without removing it from the printed circuit board. In addition to simplifying the
manufacturing flow, ISP also allows design modifications to be made in the field via
software.
Each ATF1504ASV(L) macrocell has five product terms. Each product term receives as
its inputs all signals from both the global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the five product terms as
needed to the macrocell logic gates and control signals. The PTMUX programming is
determined by the design compiler, which selects the optimum macrocell configuration.
ATF1504ASV(L)
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