EPM1270F256I5N Altera, EPM1270F256I5N Datasheet - Page 41
![IC MAX II CPLD 1270 LE 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EPM1270F256I5N
Manufacturer Part Number
EPM1270F256I5N
Description
IC MAX II CPLD 1270 LE 256-FBGA
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM1270F256I5N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
6.2ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
1270
Number Of Macrocells
980
Number Of I /o
212
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
256-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
1270
Cpld Type
FLASH
No. Of Macrocells
980
No. Of I/o's
212
Propagation Delay
7.5ns
Global Clock Setup Time
1.2ns
Frequency
304MHz
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
For Use With
544-2380 - KIT DEV MAXII W/EPM 1270N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-1675
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM1270F256I5N
Manufacturer:
ALTERA
Quantity:
165
Company:
Part Number:
EPM1270F256I5N
Manufacturer:
ALTERA
Quantity:
297
Part Number:
EPM1270F256I5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 2: MAX II Architecture
Document Revision History
Document Revision History
Table 2–8. Document Revision History
© October 2008 Altera Corporation
Date and Revision
October 2008,
version 2.2
March 2008,
version 2.1
December 2007,
version 2.0
December 2006,
version 1.7
August 2006,
version 1.6
July 2006,
vervion 1.5
February 2006,
version 1.4
August 2005,
version 1.3
December 2004,
version 1.2
June 2004,
version 1.1
Changes Made
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Table 2–8
Updated
Updated
Updated New Document Format.
Updated “Schmitt Trigger” section.
Updated “Clear and Preset Logic Control” section.
Updated “MultiVolt Core” section.
Updated “MultiVolt I/O Interface” section.
Updated Table 2–7.
Added “Referenced Documents” section.
Minor update in “Internal Oscillator” section. Added document
revision history.
Updated functional description and I/O structure sections.
Minor content and table updates.
Updated “LAB Control Signals” section.
Updated “Clear and Preset Logic Control” section.
Updated “Internal Oscillator” section.
Updated Table 2–5.
Removed Note 2 from Table 2-7.
Added a paragraph to page 2-15.
Added CFM acronym. Corrected Figure 2-19.
Table 2–4
“I/O Standards and Banks”
shows the revision history for this chapter.
and
Table
2–6.
section.
Summary of Changes
Updated document with
MAX IIZ information.
MAX II Device Handbook
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