EPM7256SQC208-7 Altera, EPM7256SQC208-7 Datasheet - Page 38
![IC MAX 7000 CPLD 256 208-PQFP](/photos/6/70/67062/544-208-pqfp_sml.jpg)
EPM7256SQC208-7
Manufacturer Part Number
EPM7256SQC208-7
Description
IC MAX 7000 CPLD 256 208-PQFP
Manufacturer
Altera
Series
MAX® 7000r
Datasheet
1.EPM7064STC44-10.pdf
(66 pages)
Specifications of EPM7256SQC208-7
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
256
Number Of Gates
5000
Number Of I /o
164
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
208-MQFP, 208-PQFP
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
16
Family Name
MAX 7000S
# Macrocells
256
Number Of Usable Gates
5000
Frequency (max)
166.7MHz
Propagation Delay Time
7.5ns
Number Of Logic Blocks/elements
16
# I/os (max)
164
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2065
EPM7256SQC208-7
EPM7256SQC208-7
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPM7256SQC208-7
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EPM7256SQC208-7N
Manufacturer:
ALTERA
Quantity:
173
MAX 7000 Programmable Logic Device Family Data Sheet
38
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Symbol
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
SU
H
FSU
FH
RD
COMB
IC
EN
GLOB
PRE
CLR
PIA
LPA
Table 26. MAX 7000 & MAX 7000E Internal Timing Parameters
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay
Slow slew rate = off
V
Output buffer and pad delay
Slow slew rate = off
V
Output buffer and pad delay
Slow slew rate = on
V
Output buffer enable delay
Slow slew rate = off
V
Output buffer enable delay
Slow slew rate = off
V
Output buffer enable delay
Slow slew rate = on
V
Output buffer disable delay
Register setup time
Register hold time
Register setup time of fast input
Register hold time of fast input
Register delay
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
Low-power adder
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
= 5.0 V
= 3.3 V
= 5.0 V or 3.3 V
= 5.0 V
= 3.3 V
= 5.0 V or 3.3 V
Parameter
(2)
(2)
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
(2)
(2)
(8)
Conditions
(7)
(2)
(7)
(2)
Min
4.0
4.0
2.0
2.0
-15
13.0
Max
10.0
2.0
2.0
2.0
8.0
1.0
6.0
6.0
3.0
4.0
5.0
8.0
6.0
7.0
6.0
1.0
1.0
6.0
6.0
1.0
4.0
4.0
2.0
Note (1)
Speed Grade
Min
4.0
4.0
–
–
-15T
15.0
Max
10.0
1.0
2.0
2.0
1.0
6.0
6.0
4.0
6.0
6.0
1.0
6.0
6.0
1.0
4.0
4.0
2.0
–
–
–
–
–
–
Min
4.0
5.0
4.0
3.0
Altera Corporation
-20
15.0
Max
14.0
10.0
11.0
10.0
3.0
3.0
4.0
9.0
2.0
8.0
8.0
4.0
5.0
6.0
9.0
1.0
1.0
8.0
8.0
3.0
4.0
4.0
3.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns