XC9572XL-7VQG44C Xilinx Inc, XC9572XL-7VQG44C Datasheet

IC CPLD 72MCRCELL 7.5NS 44VQFP

XC9572XL-7VQG44C

Manufacturer Part Number
XC9572XL-7VQG44C
Description
IC CPLD 72MCRCELL 7.5NS 44VQFP
Manufacturer
Xilinx Inc
Series
XC9500XLr
Datasheet

Specifications of XC9572XL-7VQG44C

Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
72
Number Of Gates
1600
Number Of I /o
34
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Voltage
3.3V
Memory Type
FLASH
For Use With
122-1512 - KIT DESIGN CPLD W/BATT HOLDER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Number Of Logic Elements/cells
-
Other names
122-1449

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC9572XL-7VQG44C
Manufacturer:
XilinxInc
Quantity:
3 000
Part Number:
XC9572XL-7VQG44C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC9572XL-7VQG44C
Manufacturer:
XILINX
0
Part Number:
XC9572XL-7VQG44C
Manufacturer:
XILINX
Quantity:
663
DS057 (v2.0) April 3, 2007
Features
WARNING: Programming temperature range of
T
Description
The XC9572XL is a 3.3V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
DS057 (v2.0) April 3, 2007
Product Specification
A
= 0° C to +70° C
5 ns pin-to-pin logic delays
System frequency up to 178 MHz
72 macrocells with 1,600 usable gates
Available in small footprint packages
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Optimized for high-performance 3.3V systems
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Advanced system features
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Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
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Pin-compatible with 5V-core XC9572 device in the
44-pin PLCC package and the 100-pin TQFP package
© 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
44-pin PLCC (34 user I/O pins)
44-pin VQFP (34 user I/O pins)
48-pin CSP (38 user I/O pins)
64-pin VQFP (52 user I/O pins)
100-pin TQFP (72 user I/O pins)
Pb-free available for all packages
Low power operation
5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
3.3V or 2.5V output capability
Advanced 0.35 micron feature size CMOS
Fast FLASH™ technology
In-system programmable
Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
Extra wide 54-input Function Blocks
Up to 90 product-terms per macrocell with
individual product-term allocation
Local clock inversion with three global and one
product-term clocks
Individual output enable per output pin
Input hysteresis on all user and boundary-scan pin
inputs
Bus-hold circuitry on all user pin inputs
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Endurance exceeding 10,000 program/erase
cycles
20 year data retention
ESD protection exceeding 2,000V
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
R
0
0
www.xilinx.com
0
XC9572XL High Performance
CPLD
Product Specification
cations and computing systems. It is comprised of four
54V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 5 ns. See
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of I
used:
I
where:
This calculation was derived from laboratory measurements
of an XC9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual I
value varies with the design application and should be veri-
fied during normal system operation.
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
CC
(mA) = MC
MC
PT
per macrocell
MC
PT
macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock
(~12%)
HS
LP
HS
LP
+ 0.272) + 0.04 * MC
= average number of low power product terms per
= average number of high-speed product terms
= # macrocells in low power configuration
= # macrocells in high-speed configuration
HS
(0.175*PT
CC
HS
, the following equation may be
TOG
+ 0.345) + MC
Figure 2
(MC
HS
Figure 1
+MC
for overview.
LP
LP
(0.052*PT
)* f
shows the
LP
CC
1

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XC9572XL-7VQG44C Summary of contents

Page 1

... C to +70° Description The XC9572XL is a 3.3V CPLD targeted for high-perfor- mance, low-voltage applications in leading-edge communi- © 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. ...

Page 2

... I/O 3 I/O/GCK 1 I/O/GSR 2 I/O/GTS Function Block outputs (indicated by the bold line) drive the I/O Blocks directly. 2 178 MHz 150 200 DS057_01_010102 JTAG In-System Programming Controller Controller I/O Blocks Figure 2: XC9572XL Architecture www.xilinx.com 54 Function 18 Block 1 Macrocells Function 18 Block 2 Macrocells Function 18 Block 3 Macrocells ...

Page 3

... Max; CC CCIO V = GND or 3. Min < V < 5. GND 1.0 MHz GND, No load 1.0 MHz IN www.xilinx.com XC9572XL High Performance CPLD Value –0.5 to 4.0 –0.5 to 5.5 –0.5 to 5.5 –65 to +150 +150 by 4.0V. CCINT information on the Xilinx website. For Pb-free Min Max 3.0 3.6 o ...

Page 4

... XC9572XL High Performance CPLD AC Characteristics Symbol Parameter T I/O to output valid PD T I/O setup time before GCK SU T I/O hold time after GCK H T GCK to output valid CO f Multiple FB internal operating frequency SYSTEM T I/O setup time before p-term clock input PSU T I/O hold time after p-term clock input ...

Page 5

... Internal low power logic delay LOGILP Feedback Delays T Fast CONNECT II feedback delay F Time Adders T Incremental product term allocator delay PTA T Slew-rate limited delay SLEW DS057 (v2.0) April 3, 2007 Product Specification XC9572XL High Performance CPLD XC9572XL-5 XC9572XL-7 Min Max Min Max - 1.5 - 2.3 - 1 ...

Page 6

... XC9572XL High Performance CPLD (4) XC9572XL I/O Pins Func- tion Macro- Block cell PC44 VQ44 CS48 (1) ( (1) ( (1) ( (1) ( (1) ( (3) ( Notes: 1. Global control pin. 2. GTS1 for TQ100. 3. GTS1 for PC44, VQ44, CS48, and VQ64. 4. The pin-outs are the same for Pb-free versions of packages. ...

Page 7

... R XC9572XL Global, JTAG and Power Pins Pin Type PC44 I/O/GCK1 5 I/O/GCK2 6 I/O/GCK3 7 I/O/GTS1 42 I/O/GTS2 40 I/O/GSR 39 TCK 17 TDI 15 TDO 30 TMS 16 V 3.3V 21, 41 CCINT V 2.5V/3.3V 32 CCIO GND 10, 23 Connects - Notes: 1. The pin-outs are the same for Pb-free versions of packages. DS057 (v2.0) April 3, 2007 ...

Page 8

... XC9572XL High Performance CPLD Device Part Marking and Ordering Combination Information Device Type Package Operating Range Notes: 1. Due to the small size of chip scale packages, part marking on these packages does not follow the above sample and the complete part number cannot be included in the marking. Part marking on chip scale packages by line: · ...

Page 9

... R Speed Device Ordering and (pin-to-pin Part Marking Number delay) XC9572XL-5PCG44C 5 ns XC9572XL-5VQG44C 5 ns XC9572XL-5CSG48C 5 ns XC9572XL-5VQG64C 5 ns XC9572XL-5TQG100C 5 ns XC9572XL-7PCG44C 7.5 ns XC9572XL-7VQG44C 7.5 ns XC9572XL-7CSG48C 7.5 ns XC9572XL-7VQG64C 7.5 ns XC9572XL-7TQG100C 7.5 ns XC9572XL-7PCG44I 7.5 ns XC9572XL-7VQG44I 7.5 ns XC9572XL-7CSG48I 7.5 ns XC9572XL-7VQG64I 7.5 ns XC9572XL-7TQG100I 7.5 ns XC9572XL-10PCG44C 10 ns ...

Page 10

... XC9572XL High Performance CPLD Warranty Disclaimer THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS ...

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