XC95288XL-10TQG144I Xilinx Inc, XC95288XL-10TQG144I Datasheet
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XC95288XL-10TQG144I
Specifications of XC95288XL-10TQG144I
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XC95288XL-10TQG144I Summary of contents
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... Pin-compatible with 5V core XC9500 family in common package footprints XC9536XL XC9572XL 36 72 800 1,600 3.7 3.7 3.5 3.5 178 178 www.xilinx.com XC95144XL XC95288XL 144 288 3,200 6,400 144 288 5 6 3.7 4.0 3.5 3.8 178 208 1 ...
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... Notes: 1. The letter "G" as the third character indicates a Pb-free package. DS054 (v2.5) May 22, 2009 Product Specification XC9500XL High-Performance CPLD Family Data Sheet XC9536XL XC9572XL www.xilinx.com XC95144XL XC95288XL - - - - - - - - 117 - 117 117 117 117 117 - 168 168 - 192 192 - 192 192 - 192 192 2 ...
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R 3 JTAG Port I/O I/O I/O I/O I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS Note: Function block outputs (indicated by the bold lines) drive the I/O blocks directly. Family Overview The FastFLASH XC9500XL family ...
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R operation. The XC9500XL device exhibits symmetric full 3.3V output voltage swing to allow balanced rise and fall times. Additional details can be found in the application notes listed in "Further Reading" on page Architecture Description Each XC9500XL device is ...
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R 54 Product Allocator Figure 3: XC9500XL Macrocell Within Function Block All global control signals are available to each individual macrocell, including clock, set/reset, and output enable sig- nals. As shown in Figure 4, the macrocell register clock originates from ...
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R I/O/GSR I/O/GCK1 I/O/GCK2 I/O/GCK3 Figure 4: Macrocell Clock and Set/Reset Capability DS054 (v2.5) May 22, 2009 Product Specification XC9500XL High-Performance CPLD Family Data Sheet Product Term Set Product Term Clock Product Term Reset Global Set/Reset Global Clock 1 Global ...
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R Product Term Allocator The product term allocator controls how the five direct prod- uct terms are assigned to each macrocell. For example, all five direct terms can drive the OR function as shown in Figure 5. Product Term Allocator ...
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R The product term allocator can re-assign product terms from any macrocell within the FB by combining partial sums of products over several macrocells, as shown in In this example, the incremental delay is only 2 product terms are available ...
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R The internal logic of the product term allocator is shown in Figure 8. From Upper Macrocell From Lower Macrocell DS054 (v2.5) May 22, 2009 Product Specification XC9500XL High-Performance CPLD Family Data Sheet To Upper Macrocell Product Term Allocator To ...
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R FastCONNECT II Switch Matrix The FastCONNECT II Switch Matrix connects signals to the FB inputs, as shown in Figure 9. All IOB outputs (corre- FastCONNECT II Switch Matrix DS054 (v2.5) May 22, 2009 Product Specification XC9500XL High-Performance CPLD Family ...
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... Each input buffer provides input hysteresis CCIO (50 mV typical) to help reduce system noise for input signals ) to ensure that the with slow rise or fall edges. www.xilinx.com I/O Block Bus-Hold User- 1 Programmable Ground 0 Slew Rate Control Available in XC95144XL and XC95288XL DS054_10_042101 Figure 10 for I/O 11 ...
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R Each output driver is designed to provide fast switching with minimal power noise. All output drivers in the device may be configured for driving either 3.3V CMOS levels (which are compatible with 5V TTL levels as well) or 2.5V ...
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R The XC9500XL architecture provides for superior pin-lock- ing characteristics with a combination of large number of routing switches in the FastCONNECT II switch matrix, a 54-wide input Function Block, and flexible, bidirectional product term allocation within each macrocell. These ...
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R instructions are supported in each device. Additional instructions are included for in-system programming opera- tions. Design Security XC9500XL devices incorporate advanced data security fea- tures which fully protect the programming data against unauthorized reading or inadvertent device erasure/repro- gramming. ...
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R Detailed timing information may be derived from the full tim- ing model shown in Figure 16. The values and explanations Combinatorial Logic Propagation Delay = T (a) T PSU Combinatorial Logic P-Term Clock Path Setup Time = T PSU ...
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R Power-Up Characteristics During power-up, the XC9500XL device I/Os may be unde- fined until V rises above 1 Volt. This time period is CCINT called the subthreshold region, as transistors have not yet fully turned on powered ...
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... The following table shows the revision history for this document. Date Version 09/28/98 1.0 Initial Xilinx release. 10/02/98 1.1 Figure 1 correction. 02/03/99 1.2 Included hot socket reference; revised layout; BGA package change for XC95288XL. 04/02/99 1.3 Minor typesetting corrections. 06/07/99 1.4 Minor typesetting corrections. 06/07/99 1.5 Added CS280 package. 01/25/02 1 ...
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R Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT ...