CY37128P100-125AXC Cypress Semiconductor Corp, CY37128P100-125AXC Datasheet - Page 13

• Manufacturer Part Number: CY37128P100-125AXC
• Description: IC CPLD 128 MACROCELL 100-LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: Ultra37000™r

Specifications of CY37128P100-125AXC

• Number Of Macrocells: 128
• Package / Case: 100-LQFP
• Programmable Type: In-System Reprogrammable™ (ISR™) CMOS
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of I /o: 69
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Features: Programmable
• Voltage: 5V
• Memory Type: CMOS
• Number Of Product Terms Per Macro: 16
• Maximum Operating Frequency: 125 MHz
• Delay Time: 10 ns
• Number Of Programmable I/os: 69
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Family Name: Ultra 37000
• # Macrocells: 128
• Number Of Usable Gates: 3800
• Frequency (max): 125MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 8
• # I/os (max): 69
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3710 - ADAPTER SOCKET PTG
• Number Of Logic Elements/cells: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2903; CY37128P100-125AXC

Document #: 38-03007 Rev. *E
Logic Block Diagrams
CY37512/CY37512V
TDI
TCK
TMS
JTAG Tap
Controller
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
108
120
96
12
24
36
48
60
72
84
−I/O
−I/O
0
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
131
107
119
11
23
35
47
59
71
83
95
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
(continued)
TDO
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
LOGIC
LOGIC
LOGIC
LOGIC
BLOCK
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
4
132
AO
AG
AN
AA
AB
AC
AD
AE
AF
AK
AL
AM
AP
AH
AJ
AI
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
1
Input Clock/ Input
PIM
4
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
16
36
16
36
16
36
16
36
16
36
36
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
BM
BB
BP
BO
BN
BK
BH
BG
BF
BE
BC
BA
BL
BJ
BD
BI
132
4
Ultra37000 CPLD Family
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
12 I/Os
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
144
252
240
228
216
192
180
156
132
204
168
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
−I/O
155
263
251
239
227
203
191
167
143
215
179
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