EPM2210GF256C5N Altera, EPM2210GF256C5N Datasheet - Page 55

• Manufacturer Part Number: EPM2210GF256C5N
• Description: IC MAX II CPLD 2210 LE 256-FBGA
• Manufacturer: Altera
• Series: MAX® IIr

Specifications of EPM2210GF256C5N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 2210
• Number Of Macrocells: 1700
• Number Of I /o: 204
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-FBGA
• Voltage: 1.8V
• Memory Type: FLASH
• Number Of Logic Elements/cells: 2210
• Cpld Type: FLASH
• No. Of Macrocells: 1700
• No. Of I/o's: 204
• Propagation Delay: 11.2ns
• Global Clock Setup Time: 1.9ns
• Frequency: 201.1MHz
• Rohs Compliant: Yes
• Family Name: MAX II
• # Macrocells: 1700
• Frequency (max): 1.8797GHz
• Propagation Delay Time: 11.2ns
• Number Of Logic Blocks/elements: 221
• # I/os (max): 204
• Operating Supply Voltage (typ): 1.8V
• In System Programmable: Yes
• Operating Supply Voltage (min): 1.71V
• Operating Supply Voltage (max): 1.89V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1391; EPM2210GF256C5N

Chapter 4: Hot Socketing and Power-On Reset in MAX II Devices
Power-On Reset Circuitry
Figure 4–4. ESD Protection During Negative Voltage Zap
Power-On Reset Circuitry
© October 2008 Altera Corporation
When the I/O pin receives a negative ESD zap at the pin that is less than –0.7 V (0.7 V
is the voltage drop across a diode), the intrinsic
P-Substrate/N+ drain diode is forward biased. Therefore, the discharge ESD current
path is from GND to the I/O pin, as shown in
MAX II devices have POR circuits to monitor V
power-up. The POR circuit monitors these voltages, triggering download from the
non-volatile configuration flash memory (CFM) block to the SRAM logic, maintaining
tri-state of the I/O pins (with weak pull-up resistors enabled) before and during this
process. When the MAX II device enters user mode, the POR circuit releases the I/O
pins to user functionality. The POR circuit of the MAX II (except MAX IIZ) device
continues to monitor the V
POR circuit of the MAX IIZ device does not monitor the V
device enters into user mode. More details are provided in the following sub-sections.
I/O
GND
Source
Drain
Drain
Source
CCINT
PMOS
NMOS
voltage level to detect a brown-out condition. The
Gate
Gate
P-Substrate
Figure
CCINT
N+
N+
and V
D
S
4–4.
GND
I/O
G
CCIO
CCINT
voltage levels during
voltage level after the
MAX II Device Handbook
4–5