EPM3512AQC208-10 Altera, EPM3512AQC208-10 Datasheet - Page 26
![IC MAX 3000A CPLD 512 208-PQFP](/photos/6/70/67062/544-208-pqfp_sml.jpg)
EPM3512AQC208-10
Manufacturer Part Number
EPM3512AQC208-10
Description
IC MAX 3000A CPLD 512 208-PQFP
Manufacturer
Altera
Series
MAX® 3000Ar
Datasheet
1.EPM3032ATC44-10N.pdf
(46 pages)
Specifications of EPM3512AQC208-10
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
32
Number Of Macrocells
512
Number Of Gates
10000
Number Of I /o
172
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
208-MQFP, 208-PQFP
Voltage
3.0 V ~ 3.6 V
Memory Type
EEPROM
Number Of Logic Elements/cells
32
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Other names
544-1175
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPM3512AQC208-10
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EPM3512AQC208-10N
Manufacturer:
ALTERA
Quantity:
42
Company:
Part Number:
EPM3512AQC208-10N
Manufacturer:
ALTERA44
Quantity:
3 415
Part Number:
EPM3512AQC208-10N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
MAX 3000A Programmable Logic Device Family Data Sheet
Timing Model
Figure 10. MAX 3000A Timing Model
26
Delay
Input
t
I N
Delay
PIA
t
PIA
MAX 3000A device timing can be analyzed with the Altera software, with
a variety of popular industry–standard EDA simulators and timing
analyzers, or with the timing model shown in
devices have predictable internal delays that enable the designer to
determine the worst–case timing of any design. The software provides
timing simulation, point–to–point delay prediction, and detailed timing
analysis for device–wide performance evaluation.
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin–to–pin timing delays, can be calculated
as the sum of internal parameters.
between internal and external delay parameters.
Expander Delay
Internal Output
Global Control
Control Delay
Enable Delay
Logic Array
Register
Shared
Delay
t
Delay
t
t
t
t
t
t
GLOB
SEXP
LAC
I C
EN
LAD
IOE
Expander Delay
Parallel
t
PEXP
Figure 11
Register
t
t
t
t
t
t
Delay
SU
H
PRE
CLR
RD
COMB
shows the timing relationship
Figure
Output
Delay
t
t
t
t
t
t
t
OD1
OD2
OD3
XZ
Z
Z X2
Z X3
10. MAX 3000A
X1
Altera Corporation
Delay
I/O
t
I O