EPM7128STC100-10N Altera, EPM7128STC100-10N Datasheet - Page 11
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EPM7128STC100-10N
Manufacturer Part Number
EPM7128STC100-10N
Description
IC MAX 7000 CPLD 128 100-TQFP
Manufacturer
Altera
Series
MAX® 7000r
Datasheet
1.EPM7064STC44-10.pdf
(66 pages)
Specifications of EPM7128STC100-10N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
128
Number Of Gates
2500
Number Of I /o
84
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
8
Family Name
MAX 7000S
# Macrocells
128
Number Of Usable Gates
2500
Frequency (max)
125MHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
8
# I/os (max)
84
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Cpld Type
EEPROM
No. Of Macrocells
128
No. Of I/o's
84
Propagation Delay
10ns
Global Clock Setup Time
7ns
Frequency
100MHz
Supply Voltage Range
4.75V To 5.25V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2045
EPM7128STC100-10N
EPM7128STC100-10N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7128STC100-10N
Manufacturer:
ALTERA
Quantity:
2 100
Company:
Part Number:
EPM7128STC100-10N
Manufacturer:
ALTERA41
Quantity:
300
Part Number:
EPM7128STC100-10N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
Each programmable register can be clocked in three different modes:
■
■
■
In EPM7032, EPM7064, and EPM7096 devices, the global clock signal
is available from a dedicated clock pin, GCLK1, as shown in
In MAX 7000E and MAX 7000S devices, two global clock signals are
available. As shown in
true or the complement of either of the global clock pins, GCLK1 or
GCLK2.
Each register also supports asynchronous preset and clear functions.
As shown in
product terms to control these operations. Although the
product-term-driven preset and clear of the register are active high,
active-low control can be obtained by inverting the signal within the
logic array. In addition, each register clear function can be
individually driven by the active-low dedicated global clear pin
(GCLRn). Upon power-up, each register in the device will be set to a
low state.
All MAX 7000E and MAX 7000S I/O pins have a fast input path to a
macrocell register. This dedicated path allows a signal to bypass the
PIA and combinatorial logic and be driven to an input D flipflop with
an extremely fast (2.5 ns) input setup time.
Expander Product Terms
Although most logic functions can be implemented with the five
product terms available in each macrocell, the more complex logic
functions require additional product terms. Another macrocell can
be used to supply the required logic resources; however, the
MAX 7000 architecture also allows both shareable and parallel
expander product terms (“expanders”) that provide additional
product terms directly to any macrocell in the same LAB. These
expanders help ensure that logic is synthesized with the fewest
possible logic resources to obtain the fastest possible speed.
By a global clock signal. This mode achieves the fastest clock-to-
output performance.
By a global clock signal and enabled by an active-high clock
enable. This mode provides an enable on each flipflop while still
achieving the fast clock-to-output performance of the global
clock.
By an array clock implemented with a product term. In this
mode, the flipflop can be clocked by signals from buried
macrocells or I/O pins.
Figures 3
MAX 7000 Programmable Logic Device Family Data Sheet
and 4, the product-term select matrix allocates
Figure
2, these global clock signals can be the
Figure
11
1.