EPM7128AETC144-7 Altera, EPM7128AETC144-7 Datasheet - Page 13
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EPM7128AETC144-7
Manufacturer Part Number
EPM7128AETC144-7
Description
IC MAX 7000 CPLD 128 144-TQFP
Manufacturer
Altera
Series
MAX® 7000Ar
Datasheet
1.EPM7032AELC44-10N.pdf
(64 pages)
Specifications of EPM7128AETC144-7
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
128
Number Of Gates
2500
Number Of I /o
100
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
144-TQFP, 144-VQFP
Voltage
3.3V
Memory Type
EEPROM
Number Of Logic Elements/cells
8
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Other names
544-2316
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7128AETC144-7
Manufacturer:
ALTERA
Quantity:
24
Company:
Part Number:
EPM7128AETC144-7
Manufacturer:
ALTERA
Quantity:
2 100
Part Number:
EPM7128AETC144-7
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
MAX 7000A Programmable Logic Device Data Sheet
Figure 5. MAX 7000A PIA Routing
To LAB
PIA Signals
While the routing delays of channel-based routing schemes in masked or
FPGAs are cumulative, variable, and path-dependent, the MAX 7000A
PIA has a predictable delay. The PIA makes a design’s timing
performance easy to predict.
I/O Control Blocks
The I/O control block allows each I/O pin to be individually configured
for input, output, or bidirectional operation. All I/O pins have a tri-state
buffer that is individually controlled by one of the global output enable
signals or directly connected to ground or V
.
Figure 6
shows the I/O
CC
control block for MAX 7000A devices. The I/O control block has 6 or
10 global output enable signals that are driven by the true or complement
of two output enable signals, a subset of the I/O pins, or a subset of the
I/O macrocells.
Altera Corporation
13