XC2C384-10FTG256C Xilinx Inc, XC2C384-10FTG256C Datasheet - Page 11
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XC2C384-10FTG256C
Manufacturer Part Number
XC2C384-10FTG256C
Description
IC CR-II CPLD 384MCELL 256-FBGA
Manufacturer
Xilinx Inc
Series
CoolRunner IIr
Specifications of XC2C384-10FTG256C
Operating Temperature
0°C ~ 70°C
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
9.2ns
Voltage Supply - Internal
1.7 V ~ 1.9 V
Number Of Logic Elements/blocks
24
Number Of Macrocells
384
Number Of Gates
9000
Number Of I /o
212
Mounting Type
Surface Mount
Package / Case
256-FTBGA
Features
JTAG
Voltage
1.8V
Memory Type
CMOS
No. Of Macrocells
384
No. Of I/o's
212
Propagation Delay
7.1ns
Global Clock Setup Time
2.9ns
Frequency
217MHz
Supply Voltage Range
1.7V To 1.9V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1405
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC2C384-10FTG256C
Manufacturer:
XILINX
Quantity:
41
Company:
Part Number:
XC2C384-10FTG256C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC2C384-10FTG256C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Timing Model
Figure 11
represents one aspect of the overall architecture from a tim-
ing viewpoint. Each little block is a time delay that a signal
incurs if the signal passes through such a resource. Timing
reports are created by tallying the incremental signal delays
as signals progress within the CPLD. Software creates the
timing reports after a design has been mapped onto the
Table 6: Timing Parameter Definitions
DS090 (v3.1) September 11, 2008
Product Specification
Buffer Delays
T
T
T
T
T
T
T
T
P-term Delays
T
T
T
OUT
Symbol
lN
DIN
GCK
GSR
GTS
EN
SLEW
CT
LOGI1
LOGI2
Note: Always refer to the timing report in ISE Software for accurate timing values for paths.
shows the CoolRunner-II CPLD timing model. It
T
T
T
T
R
T
GCK
GSR
GTS
DIN
IN
Input Buffer Delay
Direct data register input delay
Global clock (GCK) buffer delay
Global set/reset (GSR) buffer delay
Global output enable (GTS) buffer delay
Output buffer delay
Output buffer enable/disable delay
Output buffer slew rate control delay
Control Term delay (single PT or FB-CT)
Single P-term logic delay
Multiple P-term logic delay adder
T
T
T
T
T
HYS
HYS
HYS
HYS
HYS
Parameter
Figure 11: CoolRunner-II CPLD Timing Model
T
T
CT
LOGI1
T
LOGI2
www.xilinx.com
specific part, and knows the specific delay values for a given
speed grade. Equations for the higher level timing values
(i.e., T
the individual parameters and provides a brief definition of
their associated functions. Xilinx application note XAPP375
details the CoolRunner-II CPLD family timing with several
examples.
Table 6: Timing Parameter Definitions (Continued)
D/T
CE
Macrocell Delays
T
T
T
T
T
T
T
T
Feedback Delays
T
T
S/R
AOI
OEM
Symbol
PDI
SUI
HI
ECSU
ECHO
COI
HYS
F
T
SUI
T
T
PDI
PD
T
T
T
F
ECSU
ECHO
AOI
T
T
COI
and F
HI
Macrocell input to output valid
Macro register setup before clock
Macro register hold after clock
Macro register enable clock setup time
Macro register enable clock hold time
Macro register clock to output valid
Macro register set/reset to output valid
Hysteresis selection delay adder
Feedback delay
Macrocell to Global OE delay
SYSTEM
) are available.
T
OUT
T
OEM
CoolRunner-II CPLD Family
Parameter
T
EN
Table 6
XAPP375_03_010303
T
summarizes
SLEW
11