EPM3032ATC44-7 Altera, EPM3032ATC44-7 Datasheet - Page 5
![IC MAX 3000A CPLD 32 44-TQFP](/photos/6/70/67053/544-44-tqfp_sml.jpg)
EPM3032ATC44-7
Manufacturer Part Number
EPM3032ATC44-7
Description
IC MAX 3000A CPLD 32 44-TQFP
Manufacturer
Altera
Series
MAX® 3000Ar
Datasheet
1.EPM3032ATC44-10N.pdf
(46 pages)
Specifications of EPM3032ATC44-7
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
2
Number Of Macrocells
32
Number Of Gates
600
Number Of I /o
34
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Voltage
3.0 V ~ 3.6 V
Memory Type
EEPROM
Number Of Logic Elements/cells
2
Family Name
MAX 3000A
# Macrocells
32
Number Of Usable Gates
600
Frequency (max)
166.67MHz
Propagation Delay Time
7.5ns
Number Of Logic Blocks/elements
2
# I/os (max)
34
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
44
Package Type
TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1153
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM3032ATC44-7
Manufacturer:
ALTERA
Quantity:
30
Part Number:
EPM3032ATC44-7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EPM3032ATC44-7N/I44-10N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 1. MAX 3000A Device Block Diagram
Note:
(1)
Altera Corporation
EPM3032A, EPM3064A, EPM3128A, and EPM3256A devices have six output enables. EPM3512A devices have
10 output enables.
INPUT/OE2/GCLK2
INPUT/GCLK1
INPUT/GCLRn
INPUT/OE1
2 to 16 I/O
2 to 16 I/O
6 or 10 Output Enables (1)
Control
Control
Block
Block
I/O
I/O
Logic Array Blocks
The MAX 3000A device architecture is based on the linking of
high–performance LABs. LABs consist of 16–macrocell arrays, as shown
in
that is fed by all dedicated input pins, I/O pins, and macrocells.
Each LAB is fed by the following signals:
■
■
6 or 10
6 or 10
Figure
2 to
16
2 to
16
36 signals from the PIA that are used for general logic inputs
Global controls that are used for secondary register functions
LAB A
LAB C
1. Multiple LABs are linked together via the PIA, a global bus
Macrocells
Macrocells
33 to 48
1 to 16
MAX 3000A Programmable Logic Device Family Data Sheet
2 to 16
2 to 16
16
16
36
36
PIA
36
36
2 to 16
2 to 16
16
16
Macrocells
Macrocells
17 to 32
49 to 64
LAB D
LAB B
6 or 10 Output Enables (1)
2 to
16
2 to
16
Control
Control
Block
Block
I/O
I/O
6 or 10
6 or 10
2 to 16 I/O
2 to 16 I/O
5