EPM7064BTC100-5 Altera, EPM7064BTC100-5 Datasheet - Page 22
![IC MAX 7000 CPLD 64 100-TQFP](/photos/6/70/67055/544-100-tqfp_sml.jpg)
EPM7064BTC100-5
Manufacturer Part Number
EPM7064BTC100-5
Description
IC MAX 7000 CPLD 64 100-TQFP
Manufacturer
Altera
Series
MAX® 7000Br
Datasheet
1.EPM7256BFC256-7.pdf
(66 pages)
Specifications of EPM7064BTC100-5
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
5.0ns
Voltage Supply - Internal
2.375 V ~ 2.625 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
68
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
2.5V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Available stocks
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Part Number
Manufacturer
Quantity
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MAX 7000B Programmable Logic Device Data Sheet
22
Programmable
Speed/Power
Control
Output
Configuration
MAX 7000B devices offer a power-saving mode that supports low-power
operation across user-defined signal paths or the entire device. This
feature allows total power dissipation to be reduced by 50% or more,
because most logic applications require only a small fraction of all gates to
operate at maximum frequency.
The designer can program each individual macrocell in a MAX 7000B
device for either high-speed or low-power operation. As a result, speed-
critical paths in the design can run at high speed, while the remaining
paths can operate at reduced power. Macrocells that run at low power
incur a nominal timing delay adder (t
t
MAX 7000B device outputs can be programmed to meet a variety of
system-level requirements.
MultiVolt I/O Interface
The MAX 7000B device architecture supports the MultiVolt I/O interface
feature, which allows MAX 7000B devices to connect to systems with
differing supply voltages. MAX 7000B devices in all packages can be set
for 3.3-V, 2.5-V, or 1.8-V pin operation. These devices have one set of V
pins for internal operation and input buffers (VCCINT), and another set for
I/O output drivers (VCCIO).
The VCCIO pins can be connected to either a 3.3-V, 2.5-V, or 1.8-V power
supply, depending on the output requirements. When the VCCIO pins are
connected to a 1.8-V power supply, the output levels are compatible with
1.8-V systems. When the VCCIO pins are connected to a 2.5-V power
supply, the output levels are compatible with 2.5-V systems. When the
VCCIO pins are connected to a 3.3-V power supply, the output high is at
3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices
operating with V
adder.
Table 10
CPPW
, t
EN
describes the MAX 7000B MultiVolt I/O support.
, and t
SEXP
CCIO
parameters.
levels of 2.5 V or 1.8 V incur a nominal timing delay
LPA
) for the t
LAD
Altera Corporation
, t
LAC
, t
IC
, t
ACL
,
CC