EPM7128SQC100-15N Altera, EPM7128SQC100-15N Datasheet - Page 34
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EPM7128SQC100-15N
Manufacturer Part Number
EPM7128SQC100-15N
Description
IC MAX 7000 CPLD 128 100-PQFP
Manufacturer
Altera
Series
MAX® 7000r
Datasheet
1.EPM7064STC44-10.pdf
(66 pages)
Specifications of EPM7128SQC100-15N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
15.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
128
Number Of Gates
2500
Number Of I /o
84
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-MQFP, 100-PQFP
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
8
Family Name
MAX 7000S
# Macrocells
128
Number Of Usable Gates
2500
Frequency (max)
100MHz
Propagation Delay Time
15ns
Number Of Logic Blocks/elements
8
# I/os (max)
84
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
PQFP
Cpld Type
EEPROM
No. Of Macrocells
128
No. Of I/o's
84
Propagation Delay
15ns
Global Clock Setup Time
11ns
Frequency
76.9MHz
Supply Voltage Range
4.75V To 5.25V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2038
EPM7128SQC100-15N
EPM7128SQC100-15N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7128SQC100-15N
Manufacturer:
ALTERA40
Quantity:
13 527
Part Number:
EPM7128SQC100-15N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
MAX 7000 Programmable Logic Device Family Data Sheet
34
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Symbol
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
SU
H
FSU
FH
RD
COMB
IC
EN
GLOB
PRE
CLR
PIA
LPA
Table 22. MAX 7000 & MAX 7000E Internal Timing Parameters
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay
Slow slew rate = off
V
Output buffer and pad delay
Slow slew rate = off
V
Output buffer and pad delay
Slow slew rate = on
V
Output buffer enable delay
Slow slew rate = off
V
Output buffer enable delay
Slow slew rate = off
V
Output buffer enable delay
Slow slew rate = on
V
Output buffer disable delay
Register setup time
Register hold time
Register setup time of fast input
Register hold time of fast input
Register delay
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
Low-power adder
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
= 5.0 V
= 3.3 V
= 5.0 V or 3.3 V
= 5.0 V
= 3.3 V
= 5.0 V or 3.3 V
Parameter
(2)
(2)
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
(2)
(2)
(8)
C1 = 5 pF
Conditions
(7)
(2)
(7)
(2)
MAX 7000E (-10P) MAX 7000 (-10)
Min
2.0
3.0
3.0
0.5
Note (1)
11.0
Max
Speed Grade
0.5
0.5
1.0
5.0
0.8
5.0
5.0
2.0
1.5
2.0
5.5
5.0
5.5
9.0
5.0
2.0
2.0
5.0
5.0
1.0
3.0
3.0
1.0
MAX 7000E (-10)
Min
3.0
3.0
3.0
0.5
Altera Corporation
11.0
Max
1.0
1.0
5.0
1.0
1.0
1.0
5.0
0.8
5.0
5.0
2.0
2.0
2.5
6.0
5.0
5.5
9.0
5.0
5.0
1.0
3.0
3.0
1.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns