EPM7128SLC84-10N Altera, EPM7128SLC84-10N Datasheet - Page 38
![IC MAX 7000 CPLD 128 84-PLCC](/photos/6/70/67059/544-84-plcc_sml.jpg)
EPM7128SLC84-10N
Manufacturer Part Number
EPM7128SLC84-10N
Description
IC MAX 7000 CPLD 128 84-PLCC
Manufacturer
Altera
Series
MAX® 7000r
Datasheet
1.EPM7064STC44-10.pdf
(66 pages)
Specifications of EPM7128SLC84-10N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
128
Number Of Gates
2500
Number Of I /o
68
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
84-PLCC
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
8
Cpld Type
EEPROM
No. Of Macrocells
128
No. Of I/o's
68
Propagation Delay
10ns
Global Clock Setup Time
7ns
Frequency
100MHz
Supply Voltage Range
4.75V To 5.25V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-2033
544-2033-5
544-2033
EPM7128SLC84-10N
544-2033-5
544-2033
EPM7128SLC84-10N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7128SLC84-10N
Manufacturer:
MICROCHIP
Quantity:
3 400
Company:
Part Number:
EPM7128SLC84-10N
Manufacturer:
ALTERA30
Quantity:
2 277
Part Number:
EPM7128SLC84-10N
Manufacturer:
ALTERA
Quantity:
20 000
MAX 7000 Programmable Logic Device Family Data Sheet
38
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Symbol
IN
IO
FIN
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
SU
H
FSU
FH
RD
COMB
IC
EN
GLOB
PRE
CLR
PIA
LPA
Table 26. MAX 7000 & MAX 7000E Internal Timing Parameters
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay
Slow slew rate = off
V
Output buffer and pad delay
Slow slew rate = off
V
Output buffer and pad delay
Slow slew rate = on
V
Output buffer enable delay
Slow slew rate = off
V
Output buffer enable delay
Slow slew rate = off
V
Output buffer enable delay
Slow slew rate = on
V
Output buffer disable delay
Register setup time
Register hold time
Register setup time of fast input
Register hold time of fast input
Register delay
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
Low-power adder
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
= 5.0 V
= 3.3 V
= 5.0 V or 3.3 V
= 5.0 V
= 3.3 V
= 5.0 V or 3.3 V
Parameter
(2)
(2)
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
(2)
(2)
(8)
Conditions
(7)
(2)
(7)
(2)
Min
4.0
4.0
2.0
2.0
-15
13.0
Max
10.0
2.0
2.0
2.0
8.0
1.0
6.0
6.0
3.0
4.0
5.0
8.0
6.0
7.0
6.0
1.0
1.0
6.0
6.0
1.0
4.0
4.0
2.0
Note (1)
Speed Grade
Min
4.0
4.0
–
–
-15T
15.0
Max
10.0
1.0
2.0
2.0
1.0
6.0
6.0
4.0
6.0
6.0
1.0
6.0
6.0
1.0
4.0
4.0
2.0
–
–
–
–
–
–
Min
4.0
5.0
4.0
3.0
Altera Corporation
-20
15.0
Max
14.0
10.0
11.0
10.0
3.0
3.0
4.0
9.0
2.0
8.0
8.0
4.0
5.0
6.0
9.0
1.0
1.0
8.0
8.0
3.0
4.0
4.0
3.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns