EPM2210F324C5N Altera, EPM2210F324C5N Datasheet - Page 31

IC MAX II CPLD 2210 LE 324-FBGA

EPM2210F324C5N

Manufacturer Part Number
EPM2210F324C5N
Description
IC MAX II CPLD 2210 LE 324-FBGA
Manufacturer
Altera
Series
MAX® IIr
Datasheets

Specifications of EPM2210F324C5N

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.0ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
2210
Number Of Macrocells
1700
Number Of I /o
272
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
324-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
2210
Family Name
MAX II
# Macrocells
1700
Frequency (max)
1.8797GHz
Propagation Delay Time
11.2ns
Number Of Logic Blocks/elements
221
# I/os (max)
272
Operating Supply Voltage (typ)
2.5/3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
For Use With
P0305 - KIT MAX II MICRO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1961
EPM2210F324C5N

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Chapter 2: MAX II Architecture
I/O Structure
I/O Structure
Fast I/O Connection
© October 2008 Altera Corporation
IOEs support many features, including:
MAX II device IOEs contain a bidirectional I/O buffer.
IOE structure. Registers from adjacent LABs can drive to or be driven from the IOE’s
bidirectional I/O buffers. The Quartus II software automatically attempts to place
registers in the adjacent LAB with fast I/O connection to achieve the fastest possible
clock-to-output and registered output enable timing. For input registers, the
Quartus II software automatically routes the register to guarantee zero hold time.
You can set timing assignments in the Quartus II software to achieve desired I/O
timing.
A dedicated fast I/O connection from the adjacent LAB to the IOEs within an I/O
block provides faster output delays for clock-to-output and t
This connection exists for data output signals, not output enable signals or input
signals.
LVTTL and LVCMOS I/O standards
3.3-V, 32-bit, 66-MHz PCI compliance
Joint Test Action Group (JTAG) boundary-scan test (BST) support
Programmable drive strength control
Weak pull-up resistors during power-up and in system programming
Slew-rate control
Tri-state buffers with individual output enable control
Bus-hold circuitry
Programmable pull-up resistors in user mode
Unique output enable per pin
Open-drain outputs
Schmitt trigger inputs
Fast I/O connection
Programmable input delay
Figure
2–20,
Figure
2–21, and
Figure 2–22
illustrate the fast I/O connection.
Figure 2–19
PD
propagation delays.
shows the MAX II
MAX II Device Handbook
2–23

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