EPM2210F324I5 Altera, EPM2210F324I5 Datasheet - Page 25
![IC MAX II CPLD 2210 LE 324-FBGA](/photos/6/70/67067/544-324-fbga_sml.jpg)
EPM2210F324I5
Manufacturer Part Number
EPM2210F324I5
Description
IC MAX II CPLD 2210 LE 324-FBGA
Manufacturer
Altera
Series
MAX® IIr
Specifications of EPM2210F324I5
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.0ns
Voltage Supply - Internal
2.5V, 3.3V
Number Of Logic Elements/blocks
2210
Number Of Macrocells
1700
Number Of I /o
272
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
324-FBGA
Voltage
2.5V, 3.3V
Memory Type
FLASH
Number Of Logic Elements/cells
2210
For Use With
P0305 - KIT MAX II MICRO
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Other names
544-2269
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM2210F324I5
Manufacturer:
RENESAS
Quantity:
101
Company:
Part Number:
EPM2210F324I5
Manufacturer:
ALTERA31
Quantity:
144
Company:
Part Number:
EPM2210F324I5N
Manufacturer:
ALTERA
Quantity:
648
Chapter 2: MAX II Architecture
Global Signals
© October 2008 Altera Corporation
Figure 2–13. Global Clock Generation
Note to
(1) Any I/O pin can use a MultiTrack interconnect to route as a logic array-generated global clock signal.
The global clock network drives to individual LAB column signals, LAB column
clocks [3..0], that span an entire LAB column from the top to the bottom of the device.
Unused global clocks or control signals in a LAB column are turned off at the LAB
column clock buffers shown in
multiplexed down to two LAB clock signals and one LAB clear signal. Other control
signal types route from the global clock network into the LAB local interconnect. See
“LAB Control Signals” on page 2–5
Figure 2–13
:
Logic Array(1)
GCLK0
GCLK1
GCLK2
GCLK3
Figure
for more information.
4
2–14. The LAB column clocks [3..0] are
4
Global Clock
Network
MAX II Device Handbook
2–17