EPM7128SQC100-6 Altera, EPM7128SQC100-6 Datasheet - Page 8
![IC MAX 7000 CPLD 128 100-PQFP](/photos/6/70/67066/544-100-pqfp_sml.jpg)
EPM7128SQC100-6
Manufacturer Part Number
EPM7128SQC100-6
Description
IC MAX 7000 CPLD 128 100-PQFP
Manufacturer
Altera
Series
MAX® 7000r
Datasheet
1.EPM7064STC44-10.pdf
(66 pages)
Specifications of EPM7128SQC100-6
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
6.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
128
Number Of Gates
2500
Number Of I /o
84
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-MQFP, 100-PQFP
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
8
Family Name
MAX 7000S
# Macrocells
128
Number Of Usable Gates
2500
Frequency (max)
166.7MHz
Propagation Delay Time
6ns
Number Of Logic Blocks/elements
8
# I/os (max)
84
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2039
EPM7128SQC100-6
EPM7128SQC100-6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
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Manufacturer:
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Quantity:
5 510
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Manufacturer:
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Quantity:
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Part Number:
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MAX 7000 Programmable Logic Device Family Data Sheet
Figure 2. MAX 7000E & MAX 7000S Device Block Diagram
8
INPUT/OE2/GCLK2
INPUT/GCLRn
INPUT/GCLK1
6 to 16 I/O Pins
6 to 16 I/O Pins
INPUT/OE1
Control
Control
Block
Block
I/O
I/O
6
6
6 Output Enables
6 to16
6 to16
6 to16
6 to16
Figure 2
Logic Array Blocks
The MAX 7000 device architecture is based on the linking of high-
performance, flexible, logic array modules called logic array blocks
(LABs). LABs consist of 16-macrocell arrays, as shown in
Multiple LABs are linked together via the programmable interconnect
array (PIA), a global bus that is fed by all dedicated inputs, I/O pins, and
macrocells.
LAB A
LAB C
Macrocells
Macrocells
shows the architecture of MAX 7000E and MAX 7000S devices.
33 to 48
1 to 16
6 to16
6 to16
16
16
36
36
PIA
36
36
6 to16
6 to16
16
16
Macrocells
Macrocells
17 to 32
49 to 64
LAB D
LAB B
6 Output Enables
6 to16
6 to16
6 to16
6 to16
Control
Control
Block
Block
I/O
I/O
Altera Corporation
6
6
Figures 1
6 to 16 I/O Pins
6 to 16 I/O Pins
and 2.