EPM7128AETC100-5N Altera, EPM7128AETC100-5N Datasheet - Page 32

IC MAX 7000 CPLD 128 100-TQFP

EPM7128AETC100-5N

Manufacturer Part Number
EPM7128AETC100-5N
Description
IC MAX 7000 CPLD 128 100-TQFP
Manufacturer
Altera
Series
MAX® 7000Ar
Datasheet

Specifications of EPM7128AETC100-5N

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
5.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
128
Number Of Gates
2500
Number Of I /o
84
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
3.3V
Memory Type
EEPROM
Number Of Logic Elements/cells
8
Family Name
MAX 7000A
# Macrocells
128
Number Of Usable Gates
2500
Frequency (max)
250MHz
Propagation Delay Time
5ns
Number Of Logic Blocks/elements
8
# I/os (max)
84
Operating Supply Voltage (typ)
3.3V
In System Programmable
Yes
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2028
EPM7128AETC100-5N

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPM7128AETC100-5N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EPM7128AETC100-5N
Manufacturer:
ALTERA
0
Part Number:
EPM7128AETC100-5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EPM7128AETC100-5NS
Manufacturer:
ALTERA
0
MAX 7000A Programmable Logic Device Data Sheet
Figure 11. MAX 7000A Timing Model
32
Delay
f
Input
t
I N
Delay
PIA
t
PIA
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin-to-pin timing delays, can be calculated
as the sum of internal parameters.
between internal and external delay parameters.
See
information.
Application Note 94 (Understanding MAX 7000 Timing)
Expander Delay
Internal Output
Global Control
Control Delay
Enable Delay
Logic Array
Register
Shared
Delay
Delay
t
t
t
t
t
t
t
GLOB
SEXP
LAD
LAC
I C
EN
IOE
Expander Delay
Parallel
t
PEXP
Figure 12
Input Delay
Fast
t
F I N
Register
t
t
t
t
t
t
t
t
shows the timing relationship
Delay
SU
H
PRE
CLR
RD
COMB
FSU
FH
Altera Corporation
Output
Delay
t
t
t
t
t
t
t
OD1
OD2
OD3
XZ
Z
Z X2
Z X3
X1
for more
Delay
I/O
t
I O

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