EPM7256SQC208-10N Altera, EPM7256SQC208-10N Datasheet - Page 3
![IC MAX 7000 CPLD 256 208-PQFP](/photos/6/70/67062/544-208-pqfp_sml.jpg)
EPM7256SQC208-10N
Manufacturer Part Number
EPM7256SQC208-10N
Description
IC MAX 7000 CPLD 256 208-PQFP
Manufacturer
Altera
Series
MAX® 7000r
Datasheet
1.EPM7064STC44-10.pdf
(66 pages)
Specifications of EPM7256SQC208-10N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
256
Number Of Gates
5000
Number Of I /o
164
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
208-MQFP, 208-PQFP
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
16
Family Name
MAX 7000S
# Macrocells
256
Number Of Usable Gates
5000
Frequency (max)
125MHz
Propagation Delay Time
10ns
Number Of Logic Blocks/elements
16
# I/os (max)
164
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPM7256SQC208-10N
Manufacturer:
ALTERA
Quantity:
20 000
General
Description
Altera Corporation
EPM7032
EPM7032S
EPM7064
EPM7064S
EPM7096
EPM7128E
EPM7128S
EPM7160E
EPM7160S
EPM7192E
EPM7192S
EPM7256E
EPM7256S
Table 3. MAX 7000 Speed Grades
Device
v
v
-5
v
v
v
v
v
v
-6
■
■
The MAX 7000 family of high-density, high-performance PLDs is based
on Altera’s second-generation MAX architecture. Fabricated with
advanced CMOS technology, the EEPROM-based MAX 7000 family
provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns,
and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6,
-7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in
-5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest
Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See
for available speed grades.
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, and VeriBest
Programming support
–
–
v
v
v
v
v
v
v
v
v
v
-7
Altera’s Master Programming Unit (MPU) and programming
hardware from third-party manufacturers program all
MAX 7000 devices
The BitBlaster
parallel port download cable, and MasterBlaster
serial/universal serial bus (USB) download cable program MAX
7000S devices
-10P
v
v
MAX 7000 Programmable Logic Device Family Data Sheet
TM
Speed Grade
-10
v
v
v
v
v
v
v
v
v
v
v
serial download cable, ByteBlasterMV
-12P
v
v
-12
v
v
v
v
v
v
v
-15
v
v
v
v
v
v
v
v
v
v
v
TM
-15T
v
TM
Table 3
-20
v
v
v
v
3