EPM7128AETI144-7 Altera, EPM7128AETI144-7 Datasheet - Page 18

• Manufacturer Part Number: EPM7128AETI144-7
• Description: IC MAX 7000 CPLD 128 144-TQFP
• Manufacturer: Altera
• Series: MAX® 7000Ar

Specifications of EPM7128AETI144-7

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Logic Elements/blocks: 8
• Number Of Macrocells: 128
• Number Of Gates: 2500
• Number Of I /o: 100
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-TQFP, 144-VQFP
• Voltage: 2.5V, 3.3V
• Memory Type: CMOS
• Number Of Logic Elements/cells: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 544-2586; EPM7128AETI144-7

MAX 7000A Programmable Logic Device Data Sheet
18
Programming Times
The time required to implement each of the six programming stages can
be broken into the following two elements:
By combining the pulse and shift times for each of the programming
stages, the program or verify time can be derived as a function of the TCK
frequency, the number of devices, and specific target device(s). Because
different ISP-capable devices have a different number of EEPROM cells,
both the total fixed and total variable times are unique for a single device.
Programming a Single MAX 7000A Device
The time required to program a single MAX 7000A device in-system can
be calculated from the following formula:
where: t
The ISP times for a stand-alone verification of a single MAX 7000A device
can be calculated from the following formula:
where: t
t
t
PROG
VER
A pulse time to erase, program, or read the EEPROM cells.
A shifting time based on the test clock (TCK) frequency and the
number of TCK cycles to shift instructions, address, and data into the
device.
=
=
t
VPULSE
t
Cycle
f
t
Cycle
TCK
t
PROG
PPULSE
VER
VPULSE
PPULSE
PTCK
VTCK
+
+
Cycle VTCK
--------------------------------
Cycle
------------------------------- -
= Programming time
= Sum of the fixed times to erase, program, and
= Number of TCK cycles to program a device
= TCK frequency
f TCK
= Verify time
= Sum of the fixed times to verify the EEPROM cells
= Number of TCK cycles to verify a device
f
TCK
verify the EEPROM cells
PTCK
Altera Corporation