EPM7064BFC100-3 Altera, EPM7064BFC100-3 Datasheet - Page 17
EPM7064BFC100-3
Manufacturer Part Number
EPM7064BFC100-3
Description
IC MAX 7000 CPLD 64 100-FBGA
Manufacturer
Altera
Series
MAX® 7000Br
Datasheet
1.EPM7256BFC256-7.pdf
(66 pages)
Specifications of EPM7064BFC100-3
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
3.5ns
Voltage Supply - Internal
2.375 V ~ 2.625 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
68
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-FBGA
Voltage
2.5V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Altera Corporation
By combining the pulse and shift times for each of the programming
stages, the program or verify time can be derived as a function of the TCK
frequency, the number of devices, and specific target device(s). Because
different ISP-capable devices have a different number of EEPROM cells,
both the total fixed and total variable times are unique for a single device.
Programming a Single MAX 7000B Device
The time required to program a single MAX 7000B device in-system can
be calculated from the following formula:
where: t
The ISP times for a stand-alone verification of a single MAX 7000B device
can be calculated from the following formula:
where: t
t
t
PROG
VER
=
=
t
VPULSE
t
Cycle
f
t
Cycle
TCK
t
PROG
PPULSE
VER
VPULSE
PPULSE
PTCK
VTCK
+
+
Cycle
--------------------------------
Cycle
------------------------------- -
= Programming time
= Sum of the fixed times to erase, program, and
= Number of TCK cycles to program a device
= TCK frequency
f
= Verify time
= Sum of the fixed times to verify the EEPROM cells
= Number of TCK cycles to verify a device
TCK
f
TCK
VTCK
verify the EEPROM cells
PTCK
MAX 7000B Programmable Logic Device Data Sheet
17