XC95108-15TQ100I Xilinx Inc, XC95108-15TQ100I Datasheet - Page 6
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XC95108-15TQ100I
Manufacturer Part Number
XC95108-15TQ100I
Description
IC CPLD 108 MACROCELL 100-TQFP
Manufacturer
Xilinx Inc
Series
XC9500r
Datasheets
1.XC9572XL-10TQG100C.pdf
(1 pages)
2.XC9536-15PCG44C.pdf
(17 pages)
3.XC95108-15TQG100C.pdf
(10 pages)
Specifications of XC95108-15TQ100I
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
15.0ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Logic Elements/blocks
6
Number Of Macrocells
108
Number Of Gates
2400
Number Of I /o
81
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
5V
Memory Type
FLASH
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Other names
Q682337
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
XC9500 In-System Programmable CPLD Family
All global control signals are available to each individual
macrocell, including clock, set/reset, and output enable sig-
nals. As shown in
originates from either of three global clocks or a product
6
I/O/GCK2
I/O/GCK3
I/O/GCK1
I/O/GSR
Figure
4, the macrocell register clock
Figure 4: Macrocell Clock and Set/Reset Capability
Product Term Set
Product Term Clock
Product Term Reset
Global Set/Reset
Global Clock 1
Global Clock 2
Global Clock 3
www.xilinx.com
term clock. Both true and complement polarities of a GCK
pin can be used within the device. A GSR input is also pro-
vided to allow user registers to be set to a user-defined
state.
DS063 (v5.5) June 25, 2007
D/T
S
R
Product Specification
Macrocell
DS063_04_110501
R