XC95108-7PQ100I Xilinx Inc, XC95108-7PQ100I Datasheet - Page 16

• Manufacturer Part Number: XC95108-7PQ100I
• Description: IC CPLD 108 MCELL I-TEMP 100PQFP
• Manufacturer: Xilinx Inc
• Series: XC9500r

Specifications of XC95108-7PQ100I

• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 4.5 V ~ 5.5 V
• Number Of Logic Elements/blocks: 6
• Number Of Macrocells: 108
• Number Of Gates: 2400
• Number Of I /o: 81
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-MQFP, 100-PQFP
• Voltage: 5V
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -

XC9500 In-System Programmable CPLD Family
Power-Up Characteristics
The XC9500 devices are well behaved under all operating
conditions. During power-up each XC9500 device employs
internal circuitry which keeps the device in the quiescent
state until the V
(approximately 3.8V). During this time, all device pins and
JTAG pins are disabled and all device outputs are disabled
with the IOB pull-up resistors (~10K ohms) enabled, as
shown in
level, all user registers become initialized (typically within
100 μs for 9536, 95144, 200 μs for 95216, and 300 μs for
95288), and the device is immediately available for opera-
tion, as shown in
If the device is in the erased state (before any user pattern
is programmed), the device outputs remain disabled with
the IOB pull-up resistors enabled. The JTAG pins are
enabled to allow the device to be programmed at any time.
If the device is programmed, the device inputs and outputs
take on their configured states for normal operation. The
JTAG pins are enabled to allow device erasure or bound-
ary-scan tests at any time.
Development System Support
The XC9500 CPLD family is fully supported by the develop-
ment systems available from Xilinx and the Xilinx Alliance
Program vendors.
The designer can create the design using ABEL, schemat-
ics, equations, VHDL, or Verilog in a variety of software
front-end tools. The development system can be used to
Table 4: Timing Model Parameters
Table 5: XC9500 Device Characteristics
16
Notes:
1.
IOB Pull-up Resistors
Device Outputs
Parameter
T
SYSTEM
S = the logic span of the function, as defined in the text.
T
T
T
T
T
PSU
PCO
CO
PD
SU
Device Circuitry
Table
5. When the supply voltage reaches a safe
Propagation Delay
Global Clock Setup Time
Global Clock-to-output
Product Term Clock Setup Time
Product Term Clock-to-output
Internal System Cycle Period
CCINT
Figure
supply voltage is at a safe level
16.
Description
Quiescent State
Disabled
Enabled
www.xilinx.com
Product Term
Allocator
+ T
+ T
+ T
+ T
PTA
PTA
PTA
PTA
-
-
implement the design and generate a JEDEC bitmap which
can be used to program the XC9500 device. Each develop-
ment system includes JTAG download software that can be
used to program the devices via the standard JTAG inter-
face and a download cable.
FastFLASH Technology
An advanced CMOS Flash process is used to fabricate all
XC9500 devices. Specifically developed for Xilinx in-system
programmable CPLDs, the FastFLASH process provides
high performance logic capability, fast programming times,
and endurance of 10,000 program/erase cycles.
Erased Device Operation
*
*
*
*
3.8 V
(Typ)
3.8V
(Typ)
0V
S
S
S
S
(1)
Figure 16: Device Behavior During Power-up
Power
V
CCINT
No
Disabled
Enabled
Quiescent
Low-Power Setting
State
Macrocell
+ T
+ T
+ T
+ T
-
-
LP
LP
LP
LP
Initialization of User Registers
User Operation
Valid User Operation
DS063 (v5.5) June 25, 2007
As Configured
Product Specification
Disabled
Slew-Limited
Quiescent
+ T
+ T
+ T
Setting
Output
State
SLEW
SLEW
SLEW
–
-
-
DS063_16_110501
Power
No
R