EPM7128SQC160-15F Altera, EPM7128SQC160-15F Datasheet - Page 18
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EPM7128SQC160-15F
Manufacturer Part Number
EPM7128SQC160-15F
Description
IC MAX 7000 CPLD 128 160-PQFP
Manufacturer
Altera
Series
MAX® 7000r
Specifications of EPM7128SQC160-15F
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
15.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
128
Number Of Gates
2500
Number Of I /o
100
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
160-MQFP, 160-PQFP
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
8
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
MAX 7000 Programmable Logic Device Family Data Sheet
18
Programming Times
The time required to implement each of the six programming stages can
be broken into the following two elements:
■
■
By combining the pulse and shift times for each of the programming
stages, the program or verify time can be derived as a function of the TCK
frequency, the number of devices, and specific target device(s). Because
different ISP-capable devices have a different number of EEPROM cells,
both the total fixed and total variable times are unique for a single device.
Programming a Single MAX 7000S Device
The time required to program a single MAX 7000S device in-system can
be calculated from the following formula:
where: t
The ISP times for a stand-alone verification of a single MAX 7000S device
can be calculated from the following formula:
where: t
t PROG
t
VER
A pulse time to erase, program, or read the EEPROM cells.
A shifting time based on the test clock (TCK) frequency and the
number of TCK cycles to shift instructions, address, and data into the
device.
=
=
t
VPULSE
t
Cycle
f
t
Cycle
TCK
t PPULSE
PROG
PPULSE
VER
VPULSE
PTCK
VTCK
+
+
Cycle
--------------------------------
Cycle
------------------------------- -
= Programming time
= Sum of the fixed times to erase, program, and
= Number of TCK cycles to program a device
= TCK frequency
f
= Verify time
= Sum of the fixed times to verify the EEPROM cells
= Number of TCK cycles to verify a device
TCK
f
TCK
VTCK
verify the EEPROM cells
PTCK
Altera Corporation