EPM7032STC44-7N Altera, EPM7032STC44-7N Datasheet - Page 50
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EPM7032STC44-7N
Manufacturer Part Number
EPM7032STC44-7N
Description
IC MAX 7000 CPLD 32 44-TQFP
Manufacturer
Altera
Series
MAX® 7000r
Datasheet
1.EPM7064STC44-10.pdf
(66 pages)
Specifications of EPM7032STC44-7N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
2
Number Of Macrocells
32
Number Of Gates
600
Number Of I /o
36
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
2
Cpld Type
EEPROM
No. Of Macrocells
32
No. Of I/o's
36
Propagation Delay
7.5ns
Global Clock Setup Time
2.9ns
Frequency
175.4MHz
Supply Voltage Range
4.75V To 5.25V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-2005
EPM7032STC44-7N
EPM7032STC44-7N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPM7032STC44-7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
MAX 7000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
50
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
H
FSU
FH
RD
COMB
IC
EN
GLOB
PRE
CLR
PIA
LPA
Table 36. EPM7192S Internal Timing Parameters (Part 2 of 2)
These values are specified under the recommended operating conditions shown in
information on switching waveforms.
This minimum pulse width for preset and clear applies for both global clear and array controls. The t
must be added to this minimum width if the clear or reset signal incorporates the t
path.
This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
The f
Operating conditions: V
For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices,
these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
The t
running in the low-power mode.
LPA
MAX
Register hold time
Register setup time of fast
input
Register hold time of fast
input
Register delay
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
Low-power adder
parameter must be added to the t
values represent the highest frequency for pipelined data.
Parameter
CCIO
= 3.3 V ± 10% for commercial and industrial use.
(7)
(8)
Conditions
LAD
, t
LAC
, t
IC
, t
EN
, t
Min
1.7
2.3
0.7
SEXP
-7
, t
Max
ACL
10.0
Note (1)
1.4
1.2
3.2
3.1
2.5
2.7
2.7
2.4
, and t
Speed Grade
Min
3.0
3.0
0.5
CPPW
-10
Table
LAD
parameters for macrocells
Max
11.0
5.0
2.0
2.0
5.0
1.0
3.0
3.0
1.0
parameter into the signal
14. See
Min
Altera Corporation
4.0
2.0
1.0
Figure 13
-15
LPA
Max
13.0
1.0
1.0
6.0
6.0
1.0
4.0
4.0
2.0
parameter
for more
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns