ADSP-21061KS-133 Analog Devices Inc, ADSP-21061KS-133 Datasheet - Page 33

• Manufacturer Part Number: ADSP-21061KS-133
• Description: IC DSP CONTROLLER 32BIT 240MQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21061KS-133

• Rohs Status: RoHS non-compliant
• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 33MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP, 240-PQFP
• Frequency: 33MHz
• Supply Voltage: 5V
• Embedded Interface Type: HPI, Serial
• No. Of Mips: 50
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +85°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Asynchronous Read/Write—Host to ADSP-21061
Use these specifications for asynchronous host processor
accesses of an ADSP-21061, after the host has asserted CS and
HBR (low). After HBG is returned by the ADSP-21061, the host
Table 17. Read Cycle
1
2
Table 18. Write Cycle
1
2
Parameter
Timing Requirements
t
t
t
t
t
Switching Characteristics
t
t
t
t
Not required if RD and address are valid t
For the ADSP-21061L (3.3 V), this specification is 13.5 ns max.
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
This specification applies to the ADSP-21061KS-200 (5 V, 50 MHz) operating at t
For the ADSP-21061L (3.3 V), this specification is 13.5 ns max.
SADRDL
HADRDH
WRWH
DRDHRDY
DRDHRDY
SDATRDY
DRDYRDL
RDYPRD
HDARWH
low or by t
ADSP-21061” section in the ADSP-21061 SHARC User’s Manual, Revision 2.1.
SCSWRL
HCSWRH
SADWRH
HADWRH
WWRL
WRWH
DWRHRDY
SDATWH
HDATWH
DRDYWRL
RDYPWR
SRDYCK
HBGRCSV
after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the
Address Setup/CS Low Before RD Low
Address Hold/CS Hold Low After RD
RD/WR High Width
RD High Delay After REDY (O/D) Disable
RD High Delay After REDY (A/D) Disable
Data Valid Before REDY Disable from Low
REDY (O/D) or (A/D) Low Delay After RD Low
REDY (O/D) or (A/D) Low Pulsewidth for Read
Data Disable After RD High
CS Low Setup Before WR Low
CS Low Hold After WR High
Address Setup Before WR High
Address Hold After WR High
WR Low Width
RD/WR High Width
WR High Delay After REDY (O/D) or (A/D) Disable
Data Setup Before WR High
50 MHz, T
Data Hold After WR High
REDY (O/D) or (A/D) Low Delay After WR/CS Low
REDY (O/D) or (A/D) Low Pulsewidth for Write
REDY (O/D) or (A/D) Disable to CLKIN
CK
HBGRCSV
= 20 ns
after HBG goes low. For first access after HBR asserted, ADDR31-0 must be a non-MMS value 1/2 t
1
Rev. C | Page 33 of 56 | July 2007
1
2
CK
< 25 ns. For all other devices, use the preceding timing specification of the same name.
2
can drive the RD and WR pins to access the ADSP-21061’s
internal memory or IOP registers. HBR and HBG are assumed
low for this timing.
ADSP-21061/ADSP-21061L
Min
0
0
6
0
0
2
45 + DT
2
Min
0
0
5
2
8
6
0
3
2.5
1
15
1 + 7DT/16
5 V and 3.3 V
5 V and 3.3 V
Max
10
8
Max
11
8 + 7DT/16 ns
CLK
before RD or WR goes
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns