MSC8112TMP2400V Freescale Semiconductor, MSC8112TMP2400V Datasheet

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... Ethernet port (MII/RMII). • Flexible memory controller with three UPMs, a GPCM, a page-mode SDRAM machine, glueless interface to a variety of memories and devices, byte enables for 64- or 32-bit bus widths, © Freescale Semiconductor, Inc., 2008. All rights reserved. Document Number: MSC8112 MSC8112 FC-PBGA–431 20 mm × ...

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... Figure 30.Boundary Scan (JTAG) Timing Diagram . . . . . . . . . . . . 35 Figure 31.Test Access Port Timing Diagram . . . . . . . . . . . . . . . . . 36 Figure 32.TRST Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 36 and Figure 33.Core Power Supply Decoupling Raised Together . . 16 Figure 34.V CCSYN with CLKIN Figure 35.MSC8112 Mechanical Information, 431-pin FC-PBGA DDH Package CCSYN Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Freescale Semiconductor ...

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... The QBus interface includes a bus switch, write buffer, fetch unit, and a control unit that defines four QBus banks. In addition, the QBC handles internal memory contentions. Figure 2. StarCore MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor SC140 Extended Core 128 ...

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... This section includes diagrams of the MSC8112 package ball grid array layouts and pinout allocation tables. 1.1 FC-PBGA Ball Layout Diagrams Top and bottom views of the FC-PBGA package are shown in Figure 3 and Figure 4 with their ball location index numbers. MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev Freescale Semiconductor ...

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... GND GND V DDH HD7 HD15 HD9 HD60 DDH HD14 HD12 HD10 HD63 HD59 DD AB GND HD13 HD11 HD8 HD62 HD61 MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor Top View GND GND GND GND GND GND HCID3 GND ...

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... GND GND HD4 DDH DDH GND HD58 HD60 HD9 DDH DD V GND HD59 HD63 HD10 HD12 DDH HD56 HD57 HD61 HD62 HD8 HD11 Freescale Semiconductor GND DD EE0 TDI TRST TCK RST PO CONF RESET HA27 HA24 HA28 HA20 DD HA26 HA18 DD HA21 HA15 ...

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... GND C11 V DD C12 GND C13 V DD C14 GND C15 GND C16 GPIO30/TIMER2/TMCLK/SDA C17 GPIO2/TIMER1/CHIP_ID2/IRQ6 MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor Des. Signal Name C18 GPIO1/TIMER0/CHIP_ID1/IRQ5/ETHTXD1 C19 GPIO7/TDM3RCLK/IRQ5/ETHTXD3 C20 GPIO3/TDM3TSYN/IRQ1/ETHTXD2 C21 GPIO5/TDM3TDAT/IRQ3/ETHRXD3 C22 GPIO6/TDM3RSYN/IRQ4/ETHRXD2 D2 TDI D3 EE0 D4 ...

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... CS1 G18 BCTL0 G19 GPIO15/TDM1TSYN/DREQ1 G20 GND G21 GPIO17/TDM1TDAT/DACK1 G22 GPIO22/TDM0TCLK/DONE2/DRACK2 H2 HA20 H3 HA28 HA19 H6 TEST H7 PSDCAS/PGPL3 H8 PGTA/PUPMWAIT/PGPL4/PPBS H10 BM1/TC1/BNKSEL1 H11 ARTRY H12 AACK H13 DBB/IRQ5 H14 HTA H15 V DD H16 TT4/CS7 H17 CS4 H18 GPIO24/TDM0RSYN/IRQ14 H19 GPIO21/TDM0TSYN H20 V DD Freescale Semiconductor ...

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... K7 POE/PSDRAS/PGPL2 K8 IRQ2/BADDR30 K9 Reserved K10 GND K11 GND K12 GND K13 GND K14 CLKOUT MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor Des. Signal Name K15 V DD K16 TT2/CS5 K17 ALE K18 CS2 K19 GND K20 A26 K21 A29 ...

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... A19 R2 HD18 R3 V DDH R4 GND R5 HD22 R6 HWBS6/HDBS6/HWBE6/HDBE6/PWE6/PSDDQM6/PBS6 R7 HWBS4/HDBS4/HWBE4/HDBE4/PWE4/PSDDQM4/PBS4 R8 TSZ1 R9 TSZ3 R10 IRQ1/GBL R11 V DD R12 V DD R13 V DD R14 TT0/HA7 R15 IRQ7/DP7/DREQ4 R16 IRQ6/DP6/DREQ3 R17 IRQ3/DP3/DREQ2/EXT_BR3 R18 TS R19 IRQ2/DP2/DACK2/EXT_DBG2 R20 A17 R21 A18 R22 A16 T2 HD17 T3 HD21 T4 HD1/DSISYNC T5 HD0/SWTE Freescale Semiconductor ...

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... D14 U12 D15 U13 D17 U14 D19 U15 D22 U16 D25 U17 D26 U18 D28 U19 D31 U20 V DDH MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor Des. Signal Name U21 A12 U22 A13 V2 HD3/MODCK1 V3 V DDH V4 GND ...

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... AB3 HD13 AB4 HD11 AB5 HD8 AB6 HD62/D62 AB7 HD61/D61 AB8 HD57/D57/ETHRX_ER AB9 HD56/D56/ETHRX_DV/ETHCRS_DV AB10 HD55/D55/ETHTX_ER/reserved AB11 HD53/D53 AB12 HD50/D50 AB13 HD49/D49/ETHTXD3/reserved AB14 HD48/D48/ETHTXD2/reserved AB15 HD47/D47/ETHTXD1 AB16 HD45/D45 AB17 HD44/D44 AB18 HD41/D41/ETHRXD1 AB19 HD39/D39/reserved AB20 HD36/D36/reserved AB21 A1 AB22 V DD Freescale Semiconductor ...

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... Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the listed limits may affect device reliability or cause permanent damage. 3. Section 3.5, Thermal Considerations includes a formula for computing the chip junction temperature (T MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor CAUTION ). DD Table 2. Absolute Maximum Ratings ...

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... CCSYN V DDH Symbol Natural Convection R 26 θ θ θJB R 0.9 θJC Ψ and . V V DDH DD Value Unit 1.07 to 1.13 V 3.135 to 3.465 V –0 +0.2 V DDH –40 to 105 °C FC-PBGA × Unit 200 ft/min (1 m/s) airflow 21 °C/W 15 °C/W °C/W °C/W °C/W Freescale Semiconductor ...

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... MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines (AN2601 17% DDH DDH V GND V IL GND – 0.3 V GND – 0.7 V Figure 5. Overshoot/Undershoot Voltage for V MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor Table 5. DC Electrical Characteristics Symbol IHC V ILC DDH ...

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... Nominal Value DD 1 CLKIN Starts Toggling PORESET/TRST Asserted V /V Applied DD DDH and V DD DDH Typical Impedance (Ω PORESET V and V DD and begins to toggle as CLKIN V DDH V Nominal Level DDH V Nominal Level DD Time PORESET/TRST Deasserted Raised Together Freescale Semiconductor V DD are DDH rises. ...

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... During time interval A, V DDH The duration of interval A should be kept below 10 ms. 2. The duration of timing interval B should be kept as small as possible and less than 10 ms. MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor V = Nominal DDH V = Nominal DD 1 CLKIN starts toggling ...

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... F 40 BCLK F 40 REFCLK F 40 CLKOUT F 200 CORE Min Max — 0.3 20 see Table 8 — 3 — 150 150 — 20 100 800 1200 — 200 — 500 Freescale Semiconductor Max 100 100 100 100 300 Unit ns MHz ns ps KHz MHz MHz ps ps ...

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... Asserting initiates the power-on reset flow. PORESET and are both at their nominal levels DDH MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor Table 10. Reset Sources Description Power-On Reset Hard Reset (HRESET) (PORESET) External or Internal External only (Software Watchdog or ...

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... CNFGS, DSISYNC, DSI64, RSTCONF , deassertion to define the Reset Min Max Unit 800 — ns 160 — ns 6.17 51.2 µs 320 320 µ µs 3.08 12.8 µs 3.10 12.88 µs 3 — — ns Freescale Semiconductor ...

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... T1 T2 REFCLK T1 T2 Figure 10. Internal Tick Spacing for Memory Controller Signals MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor RSTCONF, CNFGS, DSISYNC, DSI64 CHIP_ID[0–3], BM[0–2], SWTE, MODCK[1–2] pins are sampled Host programs Reset Configuration Word MODCK[3– ...

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... MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev Table 14. AC Timing for SIU Inputs Characteristic 3 rising edge. REFCLK Ref = CLKIN at 1.1 V Units and 100 MHz 0.5 ns 3.1 ns 3.6 ns 3.0 ns 3.5 ns 4.4 ns 1.9 ns 4.2 ns 2.0 ns 8.2 ns 2.0 ns 7.9 ns 4.2 ns 5.5 ns 3.7 ns 4.8 ns 3.7 ns 4 REFCLK Freescale Semiconductor ...

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... To achieve maximum performance on the bus in single-master mode, disable the DBB signal by writing the SIUMCR[BDD] bit. See the SIU chapter in the MSC8112 Reference Manual for details. MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor Table 15. AC Timing for SIU Outputs Electrical Characteristics ...

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... MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev REFCLK 11 PSDVAL/ABB/DBB inputs inputs 14 15 PUPMWAIT input 16 17 IRQx inputs 30 Min delay for all output pins 31 PSDVAL/TEA/TA outputs 32a/b 32c BADDR outputs 33a Data bus outputs DP outputs 33b 34 35 Figure 11. SIU Timing Diagram Freescale Semiconductor ...

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... DACK/DRACK/DONE delay after the 50% level of the REFCLK rising edge signal is synchronized with The DREQ according to the timings in Table 17. Figure 13 shows synchronous peripheral interaction. MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor skew timing. Table 16. CLKOUT Skew CLKIN CLKOUT 20 Figure 12 ...

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... REFCLK 5 + (1.5 × REFCLK 5 + (2.5 × REFCLK 1 REFCLK — 8.5 2.0 — 2.2 — 2.2 — 3.2 — — 7.4 — 6.5 — 6.5 — REFCLK 5 + (1.5 × REFCLK 5 + (2.5 × REFCLK 1 — REFCLK 1.0 — 1.7 — Freescale Semiconductor Unit ...

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... HTA released at logic 0 (DCR[HTAAD end of access; used with pull-down implementation. 4. HTA released at logic 1 (DCR[HTAAD end of access; used with pull-up implementation. Figure 14. Asynchronous Single- and Dual-Strobe Modes Read Timing Diagram MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 100 101 112 102 103 107 ...

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... Used for single-strobe mode access. 2. Used for dual-strobe mode access. Figure 16. Asynchronous Broadcast Write Timing Diagram MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev 100 112 201 106 108 100 112 201 202 101 102 202 109 110 111 101 102 Freescale Semiconductor ...

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... HCID[0–4] input signals All other input signals HD[0–63] output signals HTA output signal Figure 17. DSI Synchronous Mode Signals Timing Diagram MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor Table 19. DSI Inputs in Synchronous Mode Characteristic 120 121 127 ...

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... Figure 18. TDM Inputs Signals 300 301 302 306 305 309 Figure 19. TDM Output Signals 1.1 V Core Units Min Max 1 16 — — — ns 1.3 — ns 1.0 — ns 2.8 — ns — 10.0 ns 2.5 — ns — 10.7 ns — 9.7 ns 2.5 — ns 308 307 310 Freescale Semiconductor ...

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... TIMERx Input high period 502 TIMERx Output low period 503 TIMERx Propagations delay from its clock input TIMERx (Input) TIMERx (Output) MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor Table 22. UART Timing 401 401 400 Figure 20. UART Input Timing 402 402 Figure 21 ...

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... MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev Characteristics 801 802 Valid Table 25. MII Mode Signal Timing Characteristics 803 Valid 805 Valid Figure 24. MII Mode Signal Timing Min Max Unit 10 — — ns Min Max Unit 3.5 — ns 3.5 — 14.6 ns 804 Valid Freescale Semiconductor ...

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... Measured using load. 2. Measured using load. ETHCLOCK ETHSYNC_IN ETHRXD ETHSYNC ETHTXD MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor Table 26. RMII Mode Signal Timing Characteristics 806 Valid 811 Valid Figure 25. RMII Mode Signal Timing Table 27. SMII Mode Signal Timing ...

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... Figure 27. GPIO Timing Table 29. EE Pin Timing Type Asynchronous Synchronous to Core clock EE pins Figure 28. EE Pin Timing Ref = CLKIN Unit Min Max — 6.1 ns 1.1 — ns — 5.4 ns 3.5 — ns 0.5 — ns 601 602 Min 4 core clock periods 1 core clock period Freescale Semiconductor ...

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... Figure 29. Test Clock Input Timing Diagram TCK V (Input) IL Data Inputs Data Outputs Data Outputs Figure 30. Boundary Scan (JTAG) Timing Diagram MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor Table 30. JTAG Timing Characteristics × 4); maximum 25 MHz 1 701 703 ...

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... PORESET and together not possible, raise V DDH / until / reaches its nominal voltage level. Similarly, bring both CCSYN DD CCSYN V DDH V IH 709 CLKIN / first and then bring CCSYN V going down first and DDH by more than 0 any time, including during Freescale Semiconductor must ...

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... PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the , MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor rises before V (see Figure 6), current can pass from the V DDH supply. The ESD protection diode can allow this to occur when V DDH + 0.8V. DDH level of V – ...

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... The 0.01-µF capacitor should be closest CCSYN V . These traces should be DD GND . Bypass GND to SYN SYN V CCSYN 0.01 µF should be pulled either HTA / / HWBS[1–3] HDBS[1–3] HWBE[1– PSDDQM[4–7] PBS[4– HDBS[1–3] HWBE[1–3] HDBE[1– and . TA TEA PSDVAL AACK Freescale Semiconductor V CCSYN / ...

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... SDRAM to ensure correct operation within your system design. The output delay listed in SDRAM specifications is usually given for a load of 30 pF. Scale the number to your specific board load using the typical scaling number provided by the SDRAM manufacturer. MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor . CLKIN (if SIUMCR[INTODC] is cleared), ...

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... × θ appears to be too high, either lower the ambient temperature × (θ Core Core Operating Frequency Voltage Temperature (MHz) 1.1 V –40° to 105°C 300 Eqn with natural Eqn. 2 Order Number Lead-Free Lead-Bearing MSC8112TVT2400V MSC8112TMP2400V Freescale Semiconductor ...

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... Package Information Figure 35. MSC8112 Mechanical Information, 431-pin FC-PBGA Package MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor Package Information Notes: 1. All dimensions in millimeters. 2. Dimensioning and tolerancing per ASME Y14.5M–1994. 3. Features are symmetrical about the package center lines unless dimensioned otherwise ...

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... Revision History Table 31 provides a revision history for this data sheet. Revision Date 0 5/2008 • Initial release. 1 12/2008 • Clarified the wording of note 2 in Table 23. MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev Table 31. Document Revision History Description Freescale Semiconductor ...

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... MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor Revision History 43 ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...