MSC8113TVT3600V Freescale Semiconductor, MSC8113TVT3600V Datasheet - Page 18

• Manufacturer Part Number: MSC8113TVT3600V
• Description: DSP TRI-CORE 431-FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC140 Corer

Specifications of MSC8113TVT3600V

• Interface: Ethernet, I²C, TDM, UART
• Clock Rate: 300MHz
• Non-volatile Memory: External
• On-chip Ram: 1.436MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.10V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 431-FCPBGA
• Svhc: No SVHC (15-Dec-2010)
• Base Number: 8113
• Cache On Chip L1/l2 Memory: 64KB
• Core Frequency Typ: 300MHz
• Dsp Type: Tri Core
• External Supported Memory: SRAM, SDRAM
• Interface Type: TDM, I2C, UART,
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Characteristics
2.5.4
The MSC8113 has several inputs to the reset logic:
All MSC8113 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset.
The reset status register indicates the most recent sources to cause a reset. Table 10 describes the reset sources.
18
Internal bus frequency (BLCK)
DSI clock frequency (HCLKIN)
•
•
External clock frequency (CLKIN or CLKOUT)
CLKIN frequency
BCLK frequency
Reference clock (REFCLK) frequency
Output clock (CLKOUT) frequency
SC140 core clock frequency
Note:
Phase jitter between BCLK and CLKIN
CLKIN frequency
CLKIN slope
PLL input clock (after predivider)
PLL output frequency (VCO output)
•
•
CLKOUT frequency jitter
CLKOUT phase jitter
Notes:
Core frequency = 300 MHz
Core frequency = 400 MHz
300 MHz core
400 MHz core
•
•
•
•
•
•
Power-on reset (
External hard reset (
External soft reset (
Software watchdog reset
Bus monitor reset
Host reset command through JTAG
The rise and fall time of external clocks should be 3 ns maximum
1.
2.
Reset Timing
Peak-to-peak.
Not tested. Guaranteed by design.
Characteristics
Characteristic
1
with CLKIN phase jitter of ±100 ps.
1
PORESET
Characteristic
SRESET
HRESET
MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 1
)
)
)
Table 9. System Clock Parameters
Table 7. Maximum Frequencies
Table 8. Clock Frequencies
Symbol
F
F
F
F
F
REFCLK
CLKOUT
CLKIN
CORE
BCLK
Min
200
20
40
40
40
300 MHz Device
HCLKIN ≤ (min{100 MHz, CLKOUT})
HCLKIN ≤ (min{70 MHz, CLKOUT})
Min
800
20
20
—
—
—
—
Maximum in MHz
100/133
100/133
Max
100
100
100
100
300
see Table 8
Max
1200
1600
100
200
500
0.3
3
Freescale Semiconductor
Min
200
400 MHz Device
20
40
40
40
Unit
MHz
MHz
MHz
MHz
MHz
ns
ns
ps
ps
133.3
133.3
133.3
133.3
Max
400