MSC8144VT800B Freescale Semiconductor, MSC8144VT800B Datasheet - Page 40

• Manufacturer Part Number: MSC8144VT800B
• Description: ENCRYPTION PACSUN R2.1 783FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC3400 Corer

Specifications of MSC8144VT800B

• Interface: Ethernet, I²C, SPI, TDM, UART, UTOPIA
• Clock Rate: 800MHz
• Non-volatile Memory: External
• On-chip Ram: 10.5MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.00V
• Operating Temperature: 0°C ~ 90°C
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Characteristics
2.6.4.2
Table 23
40
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)
ADDR/CMD output setup with respect to MCK
• 400 MHz
• 333 MHz
• 266 MHz
• 200 MHz
ADDR/CMD output hold with respect to MCK
• 400 MHz
• 333 MHz
• 266 MHz
• 200 MHz
MCSn output setup with respect to MCK
• 400 MHz
• 333 MHz
• 266 MHz
• 200 MHz
MCSn output hold with respect to MCK
• 400 MHz
• 333 MHz
• 266 MHz
• 200 MHz
MCK to MDQS Skew
MDQ/MECC/MDM output setup with respect to MDQS
• 400 MHz
• 333 MHz
• 266 MHz
• 200 MHz
MDQ/MECC/MDM output hold with respect to MDQS
• 400 MHz
• 333 MHz
• 266 MHz
• 200 MHz
MDQS preamble start
MDQS epilogue end
Notes:
provides the output AC timing specifications for the DDR SDRAM interface.
1.
2.
3.
4.
5.
6.
7.
The symbols used for timing specifications follow the pattern of t
inputs and t
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
t
(A) are setup (S) or output valid time. Also, t
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the
ADDR/CMD setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks by
1/2 applied cycle.
Note that t
from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). t
of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the
CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same
adjustment value. See the MSC8144 Reference Manual for a description and understanding of the timing modifications
enabled by use of these bits.
Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
All outputs are referenced to the rising edge of MCK(n) at the pins of the microprocessor. Note that t
symbol conventions described in note 1.
At recommended operating conditions with V
DDKHAS
DDR SDRAM Output AC Timing Specifications
6
4
6
symbolizes DDR timing (DD) for the time t
DDKHMH
(first two letters of functional block)(reference)(state)(signal)(state)
Parameter
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Table 23. DDR SDRAM Output AC Timing Specifications
follows the symbol conventions described in note 1. For example, t
3
3
3
2
3
5
5
DDKLDX
DDDDR
MCK
symbolizes DDR timing (DD) for the time t
(1.8 V or 2.5 V) ± 5%.
memory clock reference (K) goes from the high (H) state until outputs
Symbol
t
t
t
t
t
t
t
t
t
t
t
DDKHDS,
DDKHDX,
DDKHCS
DDKHCX
DDKHMH
DDKHMP
DDKHME
DDKHAS
DDKHAX
DDKLDS
DDKLDX
t
MCK
(first two letters of functional block)(signal)(state) (reference)(state)
for outputs. Output hold time can be read as DDR timing
1
–0.5 × t
1100
1200
1100
1200
1.95
2.40
3.15
4.20
1.85
2.40
3.15
4.20
1.95
2.40
3.15
4.20
1.95
2.40
3.15
4.20
–0.6
–0.6
Min
700
900
700
900
MCK
5
DDKHMH
DDKHMH
– 0.6
can be modified through control
describes the DDR timing (DD)
MCK
–0.5 × t
Freescale Semiconductor
memory clock reference
DDKHMP
Max
0.6
0.6
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MCK
+0.6
follows the
Unit
for
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ns
ns