ADSP-BF532SBST400 Analog Devices Inc, ADSP-BF532SBST400 Datasheet - Page 43

• Manufacturer Part Number: ADSP-BF532SBST400
• Description: IC DSP CTLR 16BIT 400MHZ 176LQFP
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF532SBST400

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 84kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 1.2/1.8/2.5/3.3V
• Operating Supply Voltage (min): 0.8/1.75V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: LQFP
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / Rohs Status: Not Compliant

Silicon Anomaly List
75.
DESCRIPTION:
The RTS instruction can fail to return correctly if placed within four execution cycles of the beginning of a subroutine. For example:
When this happens, potential bit failures in RETS will cause the processor to vector to the wrong address, which can cause invalid code to
be executed.
WORKAROUND:
If there are at least four execution cycles in the subroutine before the RTS, the CALL and RTS instructions can never align in the manner
required to encounter this problem. Since a NOP is a 1-cycle instruction, the following is a safe workaround for all potential failure cases:
Branch prediction does not factor into this scenario. Conditional jumps within the subroutine that arrive at the RTS instruction inside of 4
cycles will not result in the scenario required to cause this failure. Asynchronous events (interrupts, exceptions, and NMI) are also not
susceptible to this failure.
Beginning with VisualDSP++ 4.5 Update 6 and VisualDSP++ 5.0 Update 2, the tools include workarounds for this anomaly. The C/C++
compiler workaround avoids generating stub function code by inserting NOP instructions or an unconditional JUMP instruction before
the RTS. The JUMP workaround variant is used when optimizing for code-size (-Os) when more than two NOPs would otherwise be
required. The assembler has been modified to detect and issue a warning (ea5516) for code that could cause the anomaly to occur. The
runtime libraries and VDK support libraries have also been modified to avoid the anomaly.
These workarounds are enabled automatically in VisualDSP++ when building for affected processors. The compiler workaround can be
enabled manually using the -workaround avoid-quick-rts-371 switch. The assembler warning is controlled using the -anomaly-detect
05000371 switch. When the workarounds are enabled, the macro __WORKAROUND_AVOID_QUICK_RTS_371 is defined at compile,
assemble and link stages.
APPLIES TO REVISION(S):
0.3, 0.4, 0.5
05000371 - Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration:
CALL STUB_CODE;
...
...
...
STUB_CODE:
CALL STUB_CODE;
...
...
...
STUB_CODE:
RTS;
NOP;
NOP;
NOP;
NOP;
RTS;
// These 4 NOPs can be any combination of instructions
// that results in at least 4 core clock cycles.
NR003532D | Page 43 of 45 | July 2008
ADSP-BF531/BF532/BF533