ADSP-21369KSZ-1A Analog Devices Inc, ADSP-21369KSZ-1A Datasheet
ADSP-21369KSZ-1A
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ADSP-21369KSZ-1A Summary of contents
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... ADSP-21367/ADSP-21368/ADSP-21369 Code compatible with all other members of the SHARC family The ADSP-21367/ADSP-21368/ADSP-21369 are available with a 400 MHz core instruction rate with unique audiocen- tric peripherals such as the digital audio interface, S/PDIF transceiver, serial ports, 8-channel asynchronous sample rate converter, precision clock generators, and more ...
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... Shared memory interface (ADSP-21368 only) support provides: Glueless connection for scalable DSP multiprocessing architecture Distributed on-chip bus arbitration for parallel bus Connect four ADSP-21368 processors and global memory Four memory select lines allow multiple external memory devices Digital audio interface (DAI) includes eight serial ports, four ...
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... Thermal Characteristics ........................................ 49 256-Ball BGA_ED Pinout ......................................... 50 208-Lead MQFP Pinout ............................................ 53 Package Dimensions ................................................ 55 Surface-Mount Design .......................................... 56 Ordering Guide ...................................................... 57 ADSP-21367/ADSP-21368/ADSP-21369 REVISION HISTORY 9/07—Rev Rev. B All outstanding document errata from the previous revision of this data sheet has been corrected. Added additional information to Revised Supply Current (Internal) in Electrical Characteristics ...
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... SRU). CORE ARCHITECTURE The ADSP-21367/ADSP-21368/ADSP-21369 are code compati- ble at the assembly level with the ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-21367/ADSP-21368/ ADSP-21369processors share architectural features with the ...
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... The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the ADSP-2136x enhanced Har- vard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0– ...
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... FFFF 0x000E 1555–0x000F FFFF 1 The ADSP-21368 and ADSP-21369 processors include a customer-definable ROM block. Please contact your Analog Devices sales representative for additional details. A set of programmable timing parameters is available to config- ure the SDRAM banks to support slower memory devices. The ...
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... Bank Select 1, and support for delay line DMA. Shared External Memory The ADSP-21368 processor supports connecting to common shared external memory with other ADSP-21368 processors to create shared external bus processor systems. This support includes: • Distributed, on-chip arbitration for the shared external bus • ...
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... The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The ADSP-21367/ ADSP-21368/ADSP-21369 SPI-compatible peripheral imple- mentation also features programmable baud rate and clock phase and polarities ...
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... In conjunction with the general-purpose timer functions, auto- baud detection is supported. Timers The ADSP-21367/ADSP-21368/ADSP-21369 have a total of four timers: a core timer that can generate periodic software interrupts and three general-purpose timers that can generate periodic interrupts and be independently set to operate in one of three modes: • ...
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... VDD Target Board JTAG Emulator Connector Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21367/ ADSP-21368/ADSP-21369 processors to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor’ ...
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... ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-21367/ADSP-21368/ADSP-21369 architecture and func- tionality. For detailed information on the ADSP-2136x family core architecture and instruction set, refer to the ADSP-21368 SHARC Processor Hardware Reference and the ADSP-2136x/ADSP-2137x SHARC Processor Programming Reference. evaluation plat- ® ...
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... SDCAS O/T (pu) Table 5: The ADSP-21367/ADSP-21368/ADSP-21369 SHARC proces- sors use extensive pin multiplexing to achieve a lower pin count. For complete information on the multiplexing scheme, see the ADSP-21368 SHARC Processor Hardware Reference, “System Design” chapter. State During/ After Reset (ID = 00x) Description Pulled high/ External Address ...
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... Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the processor. Emulation Status. Must be connected to the ADSP-21367/ADSP-21368/ADSP- 21369 Analog Devices DSP Tools product line of JTAG emulator target board connectors only. ...
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... ID I (pd) 2–0 1 RPBA I (pu) 1 The pull-up is always enabled on the ADSP-21367 and ADSP-21369 processors. The pull-up on the ADSP-21368 processor is only enabled on the processor with ID 2 Pull-up can be enabled/disabled, value of pull-up cannot be programmed. State During/ After Reset (ID = 00x) Description Core/CLKIN Ratio Control. These pins set the start-up clock frequency. See Table 8 for a description of the clock configuration modes ...
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... These signals can be FLAGS or PWM or a mix of both. However, they can be selected only in groups of four. Their function is determined by the control signals FLAGS/PWM_SEL. For more information, see the ADSP-21368 SHARC Processor Hardware Reference. BOOT MODES Table 7. Boot Mode Selection BOOT_CFG1–0 ...
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... ADSP-21367/ADSP-21368/ADSP-21369 SPECIFICATIONS OPERATING CONDITIONS 1 Parameter Description V Internal (Core) Supply Voltage DDINT A Analog (PLL) Supply Voltage VDD V External (I/O) Supply Voltage DDEXT 2 V High Level Input Voltage @ Low Level Input Voltage @ High Level Input Voltage @ CLKIN 3 V Low Level Input Voltage @ CLKIN ...
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... Applies to three-statable pins with internal pull-ups: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, EMU. 10 Applies to three-statable pins with internal pull-ups disabled: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10 11 See Estimating Power Dissipation for ADSP-21368 SHARC Processors (EE-321) for further information. 12 Characterized, but not tested. 13 Applies to all signal pins ...
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... ADSP-21367/ADSP-21368/ADSP-21369 PACKAGE INFORMATION The information presented in Figure 3 the package branding for the ADSP-21367/ADSP-21368/ ADSP-21369 processors. For a complete listing of product avail- ability, see Ordering Guide on Page 57. a ADSP-2136x tppZ-cc vvvvvv.x n.n yyww country_of_origin S Figure 3. Typical Package Brand Table 9. Package Brand Information Brand Key ...
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... The shaded divider/multiplier blocks denote where clock ratios can be set through hardware or software using the power management control register (PMCTL). For more information, see the ADSP-21368 SHARC Processor Hard- ware Reference and Managing the Core PLL on Third- Generation SHARC Processors (EE-290). ...
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... ADSP-21367/ADSP-21368/ADSP-21369 Power-Up Sequencing The timing requirements for processor start-up are given in Table 13. Table 13. Power-Up Sequencing Timing Requirements (Processor Start-up) Parameter Timing Requirements t RESET Low Before V RSTVDD Before V IVDDEVDD DDINT 1 t CLKIN Valid After V CLKVDD t CLKIN Valid Before RESET Deasserted CLKRST t PLL Control Setup Before RESET Deasserted ...
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... October 2007 333 MHz 266 MHz Min Max Min Max 100 22.5 100 11. 11. 3.0 10 3.75 10 –250 +250 –250 +250 . t CKJ ADSP-2136x R1 XTAL CLKIN 22pF 22pF Y1 25.00 MHz R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL DRIVE POWER. REFER TO CRYSTAL MANUFACTURER’S SPECIFICATIONS *TYPICAL VALUES Unit ...
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... ADSP-21367/ADSP-21368/ADSP-21369 Reset Table 15. Reset Parameter Timing Requirements 1 t RESET Pulse Width Low WRST t RESET Setup Before CLKIN Low SRST Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable ...
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... DPI SRU. Therefore, the timing specifications provided below are valid at the DPI_P14–1 pins. Table 18. Timer PWM_OUT Timing Parameter Switching Characteristic t Timer Pulse Width Output PWMO DPI_P14 - 1 (TIMER2 - 0) ADSP-21367/ADSP-21368/ADSP-21369 Min 4 × t – 1 PCLK t WCTIM Figure 10. Core Timer Min 2 × t – 1.2 ...
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... ADSP-21367/ADSP-21368/ADSP-21369 Timer WDTH_CAP Timing The following timing specification applies to Timer0, Timer1, and Timer2 in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DPI_P14–1 pins through the DPI SRU. Therefore, the timing specification provided below are valid at the DPI_P14–1 pins. ...
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... PCG Output Clock Delay After PCG Trigger DTRIGCLK t PCG Frame Sync Delay After PCG Trigger DTRIGFS 1 t Output Clock Period PCGOW PH = FSxPHASE. For more information, see the ADSP-2136x SHARC Processor Hardware Reference for the ADSP-21368 Processor, “Precision Clock Generators” chapter normal mode. t STRIG DAI_Pn DPI_Pn PCG_TRIGx_I ...
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... ADSP-21367/ADSP-21368/ADSP-21369 Flags The timing specifications provided below apply to the FLAG3–0 and DPI_P14–1 pins, and the serial peripheral interface (SPI). See Table 5 on Page 12 for more information on flag use. Table 22. Flags Parameter Timing Requirement t FLAG3–0 IN Pulse Width FIPW Switching Characteristic t FLAG3– ...
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... SDRAM Interface Timing (166 MHz SDCLK) The 166 MHz access speed is for a single processor. When mul- tiple ADSP-21368 processors are connected in a shared memory system, the access speed is 100 MHz. 1 Table 23. SDRAM Interface Timing Parameter Timing Requirements t DATA Setup Before SDCLK ...
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... ADSP-21367/ADSP-21368/ADSP-21369 SDRAM Interface Enable/Disable Timing (166 MHz SDCLK) Table 24. SDRAM Interface Enable/Disable Timing Parameter Switching Characteristics t Command Disable After CLKIN Rise DSDC t Command Enable After CLKIN Rise ENSDC t SDCLK Disable After CLKIN Rise DSDCC t SDCLK Enable After CLKIN Rise ENSDCC t Address Disable After CLKIN Rise ...
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... Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode. 4 Data hold: User must meet asynchronous access mode. See HDA HDRH 5 ACK delay/setup: User must meet DAAK DSAK ADDRESS MSx t DARL RD DATA t ACK WR ADSP-21367/ADSP-21368/ADSP-21369 Min – 3.3 SDCLK W – 1 – 0.8 SDCLK . SDCLK . SDCLK ...
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... ADSP-21367/ADSP-21368/ADSP-21369 Memory Write Use these specifications for asynchronous interfacing to memo- ries. These specifications apply when the processors are the bus master accessing external memory space in asynchronous access mode. Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode. ...
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... Asynchronous Memory Interface (AMI) Enable/Disable Use these specifications for passing bus mastership between ADSP-21368 processors (BRx). Table 27. AMI Enable/Disable Parameter Switching Characteristics t Address/Control Enable After Clock Rise ENAMIAC t Data Enable After Clock Rise ENAMID t Address/Control Disable After Clock Rise DISAMIAC t Data Disable After Clock Rise ...
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... ADSP-21367/ADSP-21368/ADSP-21369 Shared Memory Bus Request Use these specifications for passing bus mastership between ADSP-21368 processors (BRx). Table 28. Multiprocessor Bus Request Parameter Timing Requirements t BRx, Setup Before CLKIN High SBRI t BRx, Hold After CLKIN High HBRI Switching Characteristics t BRx Delay After CLKIN High ...
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... Referenced to the sample edge. 2 Referenced to drive edge. 3 Minimum SPORT divisor register value. ADSP-21367/ADSP-21368/ADSP-21369 Serial port signals (SCLK, FS, data channel A, data channel B) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. ...
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... ADSP-21367/ADSP-21368/ADSP-21369 Table 31. Serial Ports—Enable and Three-State Parameter Switching Characteristics 1 t Data Enable from External Transmit SCLK DDTEN 1 t Data Disable from External Transmit SCLK DDTTE 1 t Data Enable from Internal Transmit SCLK DDTIN 1 Referenced to drive edge. Table 32. Serial Ports—External Late Frame Sync ...
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... NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. DRIVE EDGE - DAI_P20 1 SCLK (EXT) - DAI_P20 1 (DATA CHANNEL A/B) DRIVE EDGE - DAI_P20 1 SCLK (INT) - DAI_P20 1 (DATA CHANNEL A/B) ADSP-21367/ADSP-21368/ADSP-21369 SAMPLE EDGE - DAI_P20 1 (SCLK) t HFSI SFSI - DAI_P20 1 (FS) t HDRI - DAI_P20 1 (DATA CHANNEL A/B) ...
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... ADSP-21367/ADSP-21368/ADSP-21369 Input Data Port The timing requirements for the IDP are given in signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 33. IDP Parameter Timing Requirements ...
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... The timing requirements for the PDAP are provided in Table 34. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the IDP, see the IDP chapter of the ADSP-21368 SHARC Processor Hardware Table 34. Parallel Data Acquisition Port (PDAP) Parameter Timing Requirements ...
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... ADSP-21367/ADSP-21368/ADSP-21369 Pulse-Width Modulation Generators Table 35. PWM Timing Parameter Switching Characteristics t PWM Output Pulse Width PWMW t PWM Output Period PWMP PWM OUTPUTS Sample Rate Converter—Serial Input Port The SRC input signals (SCLK, FS, and SDATA) are routed from the DAI_P20–1 pins using the SRU. Therefore, the timing spec- ...
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... DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. - DAI_P20 1 (SCLK) - DAI_P20 1 (FS) - DAI_P20 1 (SDATA) ADSP-21367/ADSP-21368/ADSP-21369 and delay specification with regard to SCLK. Note that SCLK rising edge is the sampling edge and the falling edge is the drive edge. Min 4 5 SAMPLE EDGE t SRCCLK ...
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... ADSP-21367/ADSP-21368/ADSP-21369 S/PDIF Transmitter Serial data input to the S/PDIF transmitter can be formatted as 2 left justified right justified with word widths of 16, 18, 20 bits. The following sections provide timing for the transmitter. - DAI_P20 1 LRCLK - DAI_P20 1 SCLK LSB - DAI_P20 1 SDATA 2 Figure 30 shows the default I S-justified mode ...
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... Oversampling Clock (TxCLK) Switching Characteristics The S/PDIF transmitter has an oversampling clock. This TxCLK input is divided down to generate the biphase clock. Table 39. Oversampling Clock (TxCLK) Switching Characteristics Parameter TxCLK Frequency for TxCLK = 384 × FS TxCLK Frequency for TxCLK = 256 × FS Frame Rate ADSP-21367/ADSP-21368/ADSP-21369 Min ...
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... ADSP-21367/ADSP-21368/ADSP-21369 S/PDIF Receiver The following section describes timing as it relates to the S/PDIF receiver. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × FS clock. Table 40. S/PDIF Receiver Internal Digital PLL Mode Timing ...
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... SPITDM - FLAG3 0 (OUTPUT) t SDSCIM SPICLK ( (OUTPUT) SPICLK ( (OUTPUT) MOSI (OUTPUT) CPHASE = 1 MISO (INPUT) MOSI (OUTPUT) t SSPIDM CPHASE = 0 MSB MISO VALID (INPUT) ADSP-21367/ADSP-21368/ADSP-21369 applies SPICHM SPICLM SPI CLKM t t SPICL M SPICHM t t HDSPIDM D DSPIDM MSB t SSPIDM t SSPIDM t HSPIDM MSB VALID t t HDSPIDM ...
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... SPIDS Assertion to Data Out Valid (CPHASE = 0) DSOV 1 The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the ADSP-21368 SHARC Processor Hardware Reference, “Serial Peripheral Interface Port” chapter. Rev Page October 2007 ...
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... SPIDS (INPUT SPICLK ( (INPUT SPICLK ( (INPUT MISO (OUTPUT) t CPHASE = MOSI (INPUT MISO MSB (OUTPUT) CPHASE = 0 MOSI MSB VALID (INPUT) ADSP-21367/ADSP-21368/ADSP-21369 MSB MSB VALID LSB VALID LSB LSB VALID Figure 35. SPI Slave Timing Rev Page October 2007 LSB ...
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... ADSP-21367/ADSP-21368/ADSP-21369 JTAG Test Access Port and Emulation Table 43. JTAG Test Access Port and Emulation Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP 1 t System Inputs Setup Before TCK High ...
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... SW EEP ( LTAG E ( Figure 38. SDCLK1–0 Drive at Junction Temperature ADSP-21367/ADSP-21368/ADSP-21369 TEST CONDITIONS The ac signal specifications (timing parameters) appear in Table 15 on Page 22 output disable time, output enable time, and capacitive loading. The timing specifications for the SHARC apply for the voltage reference levels in Timing is measured on signals when they cross the 1 ...
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... ADSP-21367/ADSP-21368/ADSP-21369 0.049x + 1.5105 0.0482x + 1.4604 100 150 LOAD CAPACITANCE (pF) Figure 41. Typical Output Rise/Fall Time (20 Min) DDEXT 12 10 RISE y = 0.0467x + 1.6323 0.045x + 1.524 100 LOAD CAPACITANCE (pF) Figure 42. Typical Output Rise/Fall Time (20 Max) DDEXT RISE FALL 200 250 FALL 150 200 250 Rev ...
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... LOAD CAPACITANCE (pF) Figure 46. SDCLK Typical Output Delay or Hold vs. Load Capacitance (at Junction Temperature) THERMAL CHARACTERISTICS The ADSP-21367/ADSP-21368/ADSP-21369 processors are rated for performance over the temperature range specified in Operating Conditions on Page 16. Table 44 and Table 45 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-to- board measurement complies with JESD51-8 ...
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... ADSP-21367/ADSP-21368/ADSP-21369 256-BALL BGA_ED PINOUT Table 46. 256-Ball BGA_ED Pin Assignment (Numerically by Ball Number) Ball No. Signal Ball No. A01 NC B01 A02 TDI B02 A03 TMS B03 A04 CLK_CFG0 B04 A05 CLK_CFG1 B05 A06 EMU B06 A07 DAI4 B07 A08 DAI1 B08 A09 DPI14 B09 ...
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... U17 V V17 DDINT U18 V V18 DDINT U19 DATA0 V19 U20 DATA2 V20 1 The SDCLK1 signal is only available on the SBGA package. SDCLK1 is not available on the MQFP package. 2 Applies to ADSP-21368 models only. ADSP-21367/ADSP-21368/ADSP-21369 Signal Ball No. Signal V L17 V DDINT DDINT V L18 V DDINT DDINT 2 GND/ID0 ...
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... ADSP-21367/ADSP-21368/ADSP-21369 Figure 47 shows the bottom view of the BGA_ED ball configu- ration. Figure 48 shows the top view of the BGA_ED ball configuration BOTTOM VIEW KEY VDD DDINT DDEXT I/O SIGNALS GND NO CONNECT Figure 47. 256-Ball BGA_ED Ball Configuration (Bottom View VSS Rev Page October 2007 ...
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... DATA10 88 37 DATA9 89 38 DATA8 90 39 DATA7 91 40 DATA6 DDEXT 42 GND DDINT 44 DATA4 96 ADSP-21367/ADSP-21368/ADSP-21369 Signal Pin No. Signal V 105 V DDINT DDINT GND 106 GND V 107 V DDEXT DDEXT ADDR0 108 SDCAS ADDR2 109 SDRAS ADDR1 110 SDCKE ADDR4 111 SDWE ADDR3 112 ...
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... ADSP-21367/ADSP-21368/ADSP-21369 Table 47. 208-Lead MQFP Pin Assignment (Numerically by Lead Number) (Continued) Pin No. Signal Pin No. 45 DATA5 97 46 DATA2 98 47 DATA3 99 48 DATA0 100 49 DATA1 101 50 V 102 DDEXT 51 GND 103 52 V 104 DDINT Signal Pin No. Signal ADDR19 149 DAI5 ADDR20 150 V DDEXT ...
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... PACKAGE DIMENSIONS The ADSP-21367/ADSP-21368/ADSP-21369 processors are available in 256-ball RoHS compliant and leaded BGA_ED, and 208-lead RoHS compliant MQFP packages. 3.60 3.40 3.20 0.50 0.08 MAX (LEAD 0.25 COPLANARITY) VIEW A ROTATED 90° CCW ADSP-21367/ADSP-21368/ADSP-21369 0.75 4.10 0.60 MAX 0.45 208 1 SEATING PIN 1 INDICATOR ...
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... ADSP-21367/ADSP-21368/ADSP-21369 A1 BALL INDICATOR TOP VIEW DETAIL A 1.27 NOM COMPLIES WITH JEDEC STANDARD MO-192-BAL-2. Figure 50. 256-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] SURFACE-MOUNT DESIGN Table 48 is provided as an aide to PCB design. For industry- standard design recommendations, refer to IPC-7351, Generic Requirements for Surface-Mount Design and Land Pattern Standard ...
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... ADSP-21368KBPZ-2A 0°C to +70°C ADSP-21368BBP-2A –40°C to +85°C 2 ADSP-21368BBPZ-2A –40°C to +85°C 2 ADSP-21368KBPZ-3A 0°C to +70°C 2 ADSP-21369KSZ-1A 0°C to +70°C ADSP-21369KBP-2A 0°C to +70°C 2 ADSP-21369KBPZ-2A 0°C to +70°C ADSP-21369BBP-2A –40°C to +85°C 2 ADSP-21369BBPZ-2A –40°C to +85°C 2 ADSP-21369KBPZ-3A 0° ...
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... ADSP-21367/ADSP-21368/ADSP-21369 Rev Page October 2007 ...
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... ADSP-21367/ADSP-21368/ADSP-21369 Rev Page October 2007 ...
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... ADSP-21367/ADSP-21368/ADSP-21369 ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05267-0-10/07(B) Rev Page October 2007 ...